A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A method includes epitaxially growing a Ge.sub.1-xSn.sub.x channel layer over a substrate. The Ge.sub.1-xSn.sub.x channel layer is in a metastable state. A Ge.sub.1-ySn.sub.y barrier layer is epitaxially grown over the Ge.sub.1-xSn.sub.x channel layer to form a two-dimensional hole gas in the Ge.sub.1-xSn.sub.x channel layer. The Ge.sub.1-xSn.sub.x channel layer and the Ge.sub.1-ySn.sub.y barrier layer are etched to form a first opening and a second opening in the Ge.sub.1-xSn.sub.x channel layer and the Ge.sub.1-ySn.sub.y barrier layer. A first source/drain electrode and a second source/drain electrode are deposited in the first opening and the second opening, respectively. A gate electrode is formed over the Ge.sub.1-ySn.sub.y barrier layer.

A method includes epitaxially growing a Ge.sub.1-xSn.sub.x channel layer over a substrate. The Ge.sub.1-xSn.sub.x channel layer is in a metastable state. A Ge.sub.1-ySn.sub.y barrier layer is epitaxially grown over the Ge.sub.1-xSn.sub.x channel layer to form a two-dimensional hole gas in the Ge.sub.1-xSn.sub.x channel layer. The Ge.sub.1-xSn.sub.x channel layer and the Ge.sub.1-ySn.sub.y barrier layer are etched to form a first opening and a second opening in the Ge.sub.1-xSn.sub.x channel layer and the Ge.sub.1-ySn.sub.y barrier layer. A first source/drain electrode and a second source/drain electrode are deposited in the first opening and the second opening, respectively. A gate electrode is formed over the Ge.sub.1-ySn.sub.y barrier layer.

A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.

A spin orbit torque magnetoresistive random access memory (SOT MRAM) includes at least a spin current source alloy layer, a ferromagnetic free layer, and an insulation layer. The spin current source alloy layer is a nickel-tungsten alloy layer. The ferromagnetic free layer is located on the spin current source alloy layer. The insulation layer is located on the ferromagnetic free layer. Since the nickel-tungsten alloy layer has favorable perpendicular magnetic anisotropic and can maintain a high spin Hall angle, it is suitable as a spin current source for the SOT MRAM.

An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.

An MRAM structure includes a first memory unit and a second memory unit. A conductive line is disposed between the first memory unit and the second memory unit. An SOT metal conductive line contacts and electrically connects an end of the first memory unit, an end of the conductive line and an end of the second memory unit. A first switch element is electrically connected to an end of the SOT metal conductive line, and a second switch element is electrically connected to the other end of the SOT metal conductive line. A third switch element is electrically connected to the other end of the first memory unit. A fourth switch element is electrically connected to the other end of the conductive line. A fifth switch element is electrically connected to the other end of the second memory unit.

A magnetoresistive memory device and an integrated memory circuit are provided. The magnetoresistive memory device includes a magnetic tunneling junction (MTJ) and a composite spin orbit torque (SOT) channel in contact with a terminal of the MTJ. The SOT channel includes: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.

A magnetoresistive memory device and an integrated memory circuit are provided. The magnetoresistive memory device includes a magnetic tunneling junction (MTJ) and a composite spin orbit torque (SOT) channel in contact with a terminal of the MTJ. The SOT channel includes: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.

A voltage-controlled three-terminal magnon transistor is provided, including a ferroelectric layer, a magnetic layer, a generation terminal, a control terminal, a detection terminal, and a bottom electrode. After a current is inputted into the generation terminal, a magnon is generated in the magnetic layer. The detection terminal is made of a heavy metal material, which can convert the magnon in the magnetic layer into a charge flow. When a voltage pulse applied between the control terminal and the bottom electrode exceeds a critical value, non-volatile polarization and non-volatile strain states of the ferroelectric layer change, which in turn affects a transmission capability of the magnon in the magnetic layer based on a magnetoelectric coupling effect between the ferroelectric layer and the magnetic layer. In addition, a voltage signal of the detection terminal exhibits a regular loop change behavior with a change of the voltage pulse.