H10N50/20

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
20230413578 · 2023-12-21 ·

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals, where the active region includes a source, a drain, and a channel region; a word line, where the word line is connected to the channel region and extends along a first direction; a bit line, where the bit line is connected to the drain or the source and extends along a second direction, the first direction being different from the second direction; and a magnetic memory cell, connected to the source or the drain.

SPINTRONIC DEVICE, MEMORY CELL, MEMORY ARRAY AND READ AND WRITE CIRCUIT
20240013826 · 2024-01-11 ·

Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

SPINTRONIC DEVICE, MEMORY CELL, MEMORY ARRAY AND READ AND WRITE CIRCUIT
20240013826 · 2024-01-11 ·

Provided is a spintronic device, a memory cell, a memory array, and a read and write circuit applied in a field of integration technology. The spintronic device includes: a bottom electrode; a spin orbit coupling layer, arranged on the bottom electrode; at least one pair of magnetic tunnel junctions, arranged on the spin orbit coupling layer, wherein each of the magnetic tunnel junctions includes a free layer, a tunneling layer, and a reference layer arranged sequentially from bottom to top, and wherein magnetization directions of reference layers of two magnetic tunnel junctions of each pair of the magnetic tunnel junctions are opposite; and a top electrode, arranged on a reference layer of each of the magnetic tunnel junctions.

SEMICONDUCTOR DEVICE
20240040935 · 2024-02-01 ·

A semiconductor device (1) according to an embodiment of the present disclosure includes a storage element (31), an upper electrode (32), a lower electrode (33), a protective film (6), and a hydrogen adjustment region (7). The storage element (31) is embedded in an insulating layer (21). The upper electrode (32) connects the storage element (31) and a first contact (4). The lower electrode (33) is located on a side opposite to the upper electrode (32) across the storage element (31) to connect the storage element (31) and a second contact (5). The protective film (6) covers a peripheral surface of the laminated body (3) including the storage element (31), the upper electrode (32), and the lower electrode (33) except for a connection surface with the first contact (4) and a connection surface with the second contact (5). The hydrogen adjustment region (7) occludes hydrogen and is embedded in the insulating layer (21) with an insulating film (23) in the insulating layer (21) interposed between the hydrogen adjustment region (7) and the laminated body (3).

SEMICONDUCTOR DEVICE
20240040935 · 2024-02-01 ·

A semiconductor device (1) according to an embodiment of the present disclosure includes a storage element (31), an upper electrode (32), a lower electrode (33), a protective film (6), and a hydrogen adjustment region (7). The storage element (31) is embedded in an insulating layer (21). The upper electrode (32) connects the storage element (31) and a first contact (4). The lower electrode (33) is located on a side opposite to the upper electrode (32) across the storage element (31) to connect the storage element (31) and a second contact (5). The protective film (6) covers a peripheral surface of the laminated body (3) including the storage element (31), the upper electrode (32), and the lower electrode (33) except for a connection surface with the first contact (4) and a connection surface with the second contact (5). The hydrogen adjustment region (7) occludes hydrogen and is embedded in the insulating layer (21) with an insulating film (23) in the insulating layer (21) interposed between the hydrogen adjustment region (7) and the laminated body (3).

VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
20240099157 · 2024-03-21 ·

Variable resistance elements and semiconductor devices including the variable resistance elements are disclosed. In some implementations, a variable resistance element may include a variable resistance element may include a free layer having a variable magnetization direction that switches between different magnetization directions upon application of a magnetic field, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer and including a metal chalcogenide having a cubic crystal structure.

VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
20240099157 · 2024-03-21 ·

Variable resistance elements and semiconductor devices including the variable resistance elements are disclosed. In some implementations, a variable resistance element may include a variable resistance element may include a free layer having a variable magnetization direction that switches between different magnetization directions upon application of a magnetic field, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer and including a metal chalcogenide having a cubic crystal structure.

MAGNETIC MEMORY DEVICE

According to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. The electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (Mo) and ruthenium (Ru).

MAGNETIC MEMORY DEVICE

According to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. The electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (Mo) and ruthenium (Ru).

MULTI-RESISTANCE-STATE SPINTRONIC DEVICE, READ-WRITE CIRCUIT, AND IN-MEMORY BOOLEAN LOGIC OPERATOR

A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.