The present invention is directed to a magnetic memory cell including a magnetic tunnel junction (MTJ) memory element and a two-terminal bidirectional selector coupled in series between two conductive lines. The MTJ memory element includes a magnetic free layer; a magnetic reference layer; and an insulating tunnel junction layer interposed therebetween. The two-terminal bidirectional selector includes a bottom electrode; a top electrode; a load-resistance layer interposed between the bottom and top electrodes and comprising a first tantalum oxide; a first volatile switching layer interposed between the bottom and top electrodes and comprising a metal dopant and a second tantalum oxide that has a higher oxygen content than the first tantalum oxide; and a second volatile switching layer in contact with the first volatile switching layer and comprising a third tantalum oxide that has a higher oxygen content than the first tantalum oxide.

A magnetoresistive random access memory (MRAM) device having chip identification using normal operating voltages is provided. No dedicated programming is needed. Instead, programming of the MRAM device is free and random and is a result of providing a magnetic via structure sufficiently close to the magnetic free layer of the magnetic junction tunnel (MTJ) structure such that the magnetic via structure projects a magnetic field that interacts with the magnetic free layer and aligns the magnetization of the magnetic free layer with the magnetization of the magnetic via structure. Thus, the orientation of the magnetization of both the magnetic via structure and the magnetic free layer are aligned in a same direction. The magnetization of the magnetic via structure can thus be used as a physical unclonable function and the MTJ structure can be used to read out this information.

A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming a first top electrode on the MTJ stack, and then forming a second top electrode on the first top electrode. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

The present disclosure provides a semiconductor structure, including an N.sup.th metal layer over a transistor region, where N is a natural number, and a bottom electrode over the N.sup.th metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1).sup.th metal layer over the top electrode. The first width is greater than the third width.

A single-chip two-axis magnetoresistive angle sensor comprises a substrate located in an X-Y plane, a push-pull X-axis magnetoresistive angle sensor and a push-pull Y-axis magnetoresistive angle sensor located on the substrate. The push-pull X-axis magnetoresistive angle sensor comprises an X push arm and an X pull arm. The push-pull Y-axis magnetoresistive angle sensor comprises a Y push arm and a Y pull arm. Each of the X push, X pull, Y push arm, and Y pull arms comprises at least one magnetoresistive angle sensing array unit. The magnetic field sensing directions of the magnetoresistive angle sensing array units of the X push, X pull, Y push, and Y pull arms are along +X, −X, +Y and −Y directions respectively. Each magnetoresistive sensing unit comprises a TMR or GMR spin-valve having the same magnetic multi-layer film structure. A magnetization direction of an anti-ferromagnetic layer is set into a desired orientation through the use of a laser controlled magnetic annealing, and a magnetic field attenuation layer can be deposited in the surface of the magnetoresistance angle sensing unit.

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.

The present disclosure provides a domain wall magnetic tunnel junction device. Integration of input spikes pushes a domain wall within a ferromagnetic track toward a magnetic tunnel junction (MTJ). An energy gradient within the track pushes the domain wall away from the MTJ by leaking accumulated energy from the input spikes. If the integrated input spikes exceed the energy leak of the gradient within a specified time period, the domain wall reaches the MTJ and reverses its resistance, producing an output spike. The leaking energy gradient can be created by a magnetic field, a trapezoidal shape of the ferromagnetic track, or nonuniform material properties in the ferromagnetic track.

One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.