According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.

An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.

A magnetic memory of an embodiment includes: a first magnetic member including a first and second portions and extending in a first direction; a first and second wirings disposed to be apart from the first magnetic member and extending in a second direction intersecting the first direction, the first and the second wirings being separated from each other in a third direction intersecting the first and second directions, the first magnetic member being disposed to be apart from a region between the first wiring and the second wiring in the first direction; and a second magnetic member surrounding at least parts of the first and second wirings, the second magnetic member including a third portion located to be more distant from the first magnetic member, a fourth portion located to be closer to the first magnetic member, and a fifth portion located in the region.

A magnetic memory of an embodiment includes: a first magnetic member including a first and second portions and extending in a first direction; a first and second wirings disposed to be apart from the first magnetic member and extending in a second direction intersecting the first direction, the first and the second wirings being separated from each other in a third direction intersecting the first and second directions, the first magnetic member being disposed to be apart from a region between the first wiring and the second wiring in the first direction; and a second magnetic member surrounding at least parts of the first and second wirings, the second magnetic member including a third portion located to be more distant from the first magnetic member, a fourth portion located to be closer to the first magnetic member, and a fifth portion located in the region.

A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

A low temperature deposited (400° C. or less) dielectric passivation layer is formed on physically exposed surfaces of a material stack including a multilayered magnetic tunnel junction (MTJ) pillar and a top electrode. A laser anneal is then performed to improve the physical and chemical properties of the low temperature deposited dielectric passivation layer, without negatively impacting the multilayered MTJ pillar.

A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

Aspects of the invention are directed to a method of forming an integrated circuit. Both a dielectric layer and a bottom contact are formed with the bottom contact disposed at least partially in the dielectric layer. The bottom contact is subsequently recessed into the dielectric layer to cause the dielectric layer to define two sidewalls bordering regions of the bottom contact removed during recessing. Two sidewall spacers are then formed along the two sidewalls. A landing pad is formed on the recessed bottom contact and between the two sidewall spacers. Lastly, an additional feature is formed on top of the landing pad at least in part by anisotropic etching. In one or more embodiments, the additional feature includes a magnetic tunnel junction patterned at least in part by ion beam etching.

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.