H10N50/80

Highly physical ion resistive spacer to define chemical damage free sub 60 nm MRAM devices

A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

MJT based anti-fuses with low programming voltage

A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

Magnetic memory device that suppresses diffusion of elements

A magnetic memory device includes a magnetoresistance effect element including a first, second, and third ferromagnetic layer, a first non-magnetic layer between the first and second ferromagnetic layer, and a second non-magnetic layer between the second and third ferromagnetic layer. The second ferromagnetic layer is between the first and third ferromagnetic layer. The third ferromagnetic layer includes a fourth ferromagnetic layer in contact with the second non-magnetic layer, a third non-magnetic layer, and a fourth non-magnetic layer between the fourth ferromagnetic layer and the third non-magnetic layer. The first non-magnetic layer includes an oxide including magnesium (Mg). A melting point of the fourth non-magnetic layer is higher than the third non-magnetic layer.

Magnetoresistive random access memory

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Magnetoresistive random access memory

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Method of manufacturing magnetoresistive random access memory (MRAM) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Method of manufacturing magnetoresistive random access memory (MRAM) device

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Magnetic tunnel junction and magnetic memory device comprising the same

In one embodiment, the magnetic memory device includes a free layer structure having a variable magnetization direction. The free layer structure includes a first free layer, the first free layer being a first Heusler alloy; a coupling layer on the first free layer, the coupling layer including a metal oxide layer; and a second free layer on the metal oxide layer, the second free layer being a second Heusler alloy, the second Heusler alloy being different from the first Heusler alloy.

Magnetic tunnel junction and magnetic memory device comprising the same

In one embodiment, the magnetic memory device includes a free layer structure having a variable magnetization direction. The free layer structure includes a first free layer, the first free layer being a first Heusler alloy; a coupling layer on the first free layer, the coupling layer including a metal oxide layer; and a second free layer on the metal oxide layer, the second free layer being a second Heusler alloy, the second Heusler alloy being different from the first Heusler alloy.

Electric field controlled magnetoresistive random-access memory

Disclosed is an electric field-controlled magnetoresistive random-access memory (MRAM) including memory cells. The memory cell has a heterogenous double tunnel junction structure including a first tunnel junction and a second tunnel junction. The first tunnel junction includes a magnetic tunnel junction layer having a magnetization direction that changes according to spin transfer torque when an external voltage is applied, and the second tunnel junction includes an electric-field control layer that controls an electric field applied to the magnetic tunnel junction layer to induce a change in magnetic anisotropy within the magnetic tunnel junction layer. The heterogeneous tunnel junction structure combines electric field-controlled magnetic anisotropy and spin transfer torque to enable low power driving of memory cells, thereby enabling a high energy-efficient electric field-controlled MRAM.