H10N52/101

Spin current magnetization rotational element, spin-orbit torque magnetoresistance effect element, and magnetic memory
11222919 · 2022-01-11 · ·

A spin current magnetization rotational element includes: a spin-orbit torque wiring extending in a first direction; and a first ferromagnetic layer laminated in a second direction intersecting with the spin-orbit torque wiring, wherein the first ferromagnetic layer comprises a plurality of ferromagnetic constituent layers and at least one inserted layer sandwiched between adjacent ferromagnetic constituent layers, and polarities of spin Hall angles of two layers, which sandwich at least one of the ferromagnetic constituent layers among the plurality of the ferromagnetic constituent layers, differ.

Semiconductor device with integrated magnetic flux concentrator, and method for producing same

A method of producing a semiconductor substrate comprising at least one integrated magnetic flux concentrator, comprising the steps of: a) providing a semiconductor substrate having an upper surface; b) making at least one cavity in said upper surface; c) depositing one or more layers of one or more materials, including sputtering at least one layer of a soft magnetic material; d) removing substantially all of the soft magnetic material that is situated outside of the at least one cavity, while leaving at least a portion of the soft magnetic material that is inside said at least one cavity. A semiconductor substrate comprising at least one integrated magnetic flux concentrator. A sensor device or a sensor system, a current sensor device or system, a position sensor device or system, a proximity sensor device or system, an integrated transformer device or system.

Spin-orbit torque type magnetoresistance effect element, and method for producing spin-orbit torque type magnetoresistance effect element
11793088 · 2023-10-17 · ·

A spin-orbit torque type magnetoresistance effect element including a magnetoresistance effect element having a first ferromagnetic metal layer with a fixed magnetization direction, a second ferromagnetic metal layer with a varying magnetization direction, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer; and spin-orbit torque wiring that extends in a first direction intersecting with a stacking direction of the magnetoresistance effect element and that is joined to the second ferromagnetic metal layer; wherein the magnetization of the second ferromagnetic metal layer is oriented in the stacking direction of the magnetoresistance effect element; and the second ferromagnetic metal layer has shape anisotropy, such that a length along the first direction is greater than a length along a second direction orthogonal to the first direction and to the stacking direction.

Hall sensor with dielectric isolation and p-n junction isolation

A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.

Semiconductor device
11165014 · 2021-11-02 · ·

A semiconductor device includes a semiconductor substrate; a vertical Hall element including a magnetosensitive portion, and formed in the semiconductor substrate; and an excitation wiring provided above a surface of the semiconductor substrate and apart from the magnetosensitive portion. The excitation wiring is formed of a single wiring with a plurality of turns. The excitation wiring includes a plurality of main wiring portions arranged side by side, and apart from one another in an overlapping region that overlaps the magnetosensitive portion as viewed in plan view from a direction orthogonal to the surface of the semiconductor substrate; and auxiliary wiring portions connecting each of the plurality of main wiring portions to one another in series.

CURRENT SENSOR INTEGRATED CIRCUIT WITH A DUAL GAUGE LEAD FRAME

A current sensor IC includes a unitary lead frame having a primary conductor with a first thickness and a secondary lead having a second thickness less than the first thickness. A semiconductor die adjacent to the primary conductor includes a magnetic field sensing circuit to sense a magnetic field associated with the current and generate a secondary signal indicative of the current. An insulation structure is disposed between the primary conductor and the die. A mold material encloses a first portion of the secondary lead and a second portion of the secondary lead that is exposed outside of the package has the second thickness. A method of manufacturing a current sensor IC includes providing a unitary lead frame sheet having a first thickness, decreasing a thickness of a portion of the sheet to provide a first portion with the first thickness and a second portion with a smaller thickness, and stamping the sheet to form a repeating lead frame pattern, with each pattern including a primary conductor formed from the first portion and secondary leads formed from the second portion.

SPIN-ORBIT READOUT USING TRANSITION METAL DICHALCOGENIDES AND PROXIMITIZED GRAPHENE

In one embodiment, an integrated circuit die includes: a first layer comprising a magnetoelectric material; a second layer comprising a monolayer transition metal dichalcogenide (TMD); a magnet between the first layer and the second layer, wherein the magnet has perpendicular magnetic anisotropy; a first conductive trace coupled to the first layer; and a second conductive trace coupled to the magnet.

Semiconductor device and method of forming the same

A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Nanoscale strain engineering of graphene devices with tuneable electronic correlation for quantum valleytronics and spintronics

A strain engineered material including a monolayer graphene sheet comprising an array of wrinkles induced by deformations in the graphene sheet, the deformations formed by a lattice of underlying nanostructures on a substrate. The lattice of nanostructures comprises rows of the nanostructures and each of the wrinkles comprise a ridge aligned on top of a different one of the rows and along an alignment direction defined by the rows. The deformations pattern a strain distribution in the graphene sheet that induces a periodically varying pseudo magnetic field distribution ranging between a positive value and a negative values. The periodically varying pseudo magnetic field distribution has field magnitude minima located parallel to and between the ridges and field magnitude maxima located near to and parallel to each of the ridges and can be designed for various valleytronic and spintronic device applications.

Semiconductor device package with isolated semiconductor die and electric field curtailment
11621215 · 2023-04-04 · ·

In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.