A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.

A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.

An electronic device includes a first surface and a second surface opposite the first surface and intended to connect a first electronic component to a second electronic component located on the first surface by at least one conductor track, the conductor track including a plurality of sections disposed one after the other in such a way as to form the conductor track, each section being constituted of a superconducting material chosen in such a way as to form with the section that follows it, if such a section exists, and the section that precedes it, if such a section exists, an acoustic mismatching interface (or Kapitza interface).

Example implementations include a method of manufacturing a quantum computing device, by depositing a superconducting electrode layer on at least a portion of a superconducting wafer, forming a plurality of electrode pads on the superconducting electrode layer, depositing an electrode bonding interlayer on the electrode pads, singulating the superconducting wafer into a first superconducting die including a first electrode pad among the plurality and a second superconducting die including a second electrode pad among the plurality, and integrating the first superconducting die with the second superconducting die at a bonding interface between the first electrode pad and the second electrode pad.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

Techniques related to vertical silicon-on-metal superconducting quantum interference devices and method of fabricating the same are provided. Also provided are associated flux control and biasing circuitry. A superconductor structure can comprise a silicon-on-metal substrate that can comprise a first superconducting layer, comprising a first superconducting material, between a first crystalline silicon layer and a second crystalline silicon layer. The superconducting structure can also comprise a first via comprising a first Josephson junction and a second via comprising a second Josephson junction. The first via and the second via can be formed between the first superconducting layer and a second superconducting layer, comprising a second superconducting material. An electrical loop around a defined area of the second crystalline silicon layer can comprise the first via comprising the first Josephson junction, the second via comprising the second Josephson junction, the first superconducting layer, and the second superconducting layer.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

A method for manufacturing a superconductor is described. A metal assembly precursor can be formed within a hollow copper support element. Forming the metal assembly precursor within a hollow copper support element by positioning a plurality of conductor elements about a core including Sn to provide a first plurality of inner interstitial spaces between the plurality of conductor elements between the core and conductor elements and a second plurality of outer interstitial spaces between the hollow copper support element and the core, the plurality of conductor elements including unreacted Nb. The metal assembly precursor can be reduced via cold drawing to produce a reduced metal assembly. The reduced metal assembly can be reaction heat treated so that the unreacted Nb undergoes a phase transformation to a reacted superconductor.

A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively. The first, second, fourth and fifth electric potentials are controllable to define an electrical potential well to confine quantum charge carriers in an elongate quantum dot beneath the elongate channel. The fourth and fifth electric potentials and the position of the fourth and fifth metallic structures define first and second ends of the elongate channel respectively. The width of the electrical potential well is defined by the position of the first and second metallic structures and their corresponding electric potentials; and the length of the electrical potential well is defined by the position of the fourth and fifth metallic structures and their corresponding electric potentials. The third electric potential is controllable to adjust quantum charge carrier energy levels in the electrical potential well.