Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furthermore, provided herein are articles comprising one or more compositions of the invention and method of manufacturing thereof.

An electronic device includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material includes a first wire and a loop that is (1) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state.

Techniques are described herein that are capable of progressively thermally drying a quantum circuit. An inert gas is progressively heated by a heater element to provide a heated inert gas. Heated ambient air and the heated inert gas combine in a heating channel, causing a combination of the heated ambient air and the heated inert gas to flow into a probe compartment to progressively thermally dry a quantum circuit therein. A flow rate of the inert gas is controlled to cause the combination to have a relative humidity less than or equal to a threshold. A temperature of the heater element may be controlled to be approximately equal to a progressively increasing target temperature within a tolerance of 3.0° C. Heating of the inert gas may be initiated based on detection of the inert gas, and the flow and heating of the inert gas may be automatically discontinued.

There is provided a method for fabricating a device. On a top surface of a substrate, a first layer of a first deposition material is formed. The first layer of the first deposition material is patterned to create a seed pattern of remaining first deposition material. Homoepitaxy is used to grow a second layer of the first deposition material on the seed pattern.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb.sub.2O.sub.5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.

Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb.sub.2O.sub.5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.