Patent classifications
H10N60/10
Cryogenic refrigeration for low temperature devices
A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
PARTICLE DETECTOR, PARTICLE DETECTION APPARATUS, AND PARTICLE DETECTION METHOD
A particle detector according to one embodiment includes: superconductive lines, conductive lines, insulating films, a first detection circuit, and a second detection circuit. The superconductive lines extend in a first direction and are arranged in a second direction intersecting the first direction. The conductive lines extend in a third direction different from the first direction and are arranged in a fourth direction intersecting the third direction. The insulating films are each interposed at an intersection point between one of the superconductive lines and one of the conductive lines. The first detection circuit detects a voltage change occurring in the superconductive lines. The second detection circuit detects a current or a voltage generated in the conductive lines when the voltage change occurs.
MICROMACHINED SUPERCONDUCTING INTERCONNECT IN SILICON
A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.
MICROMACHINED SUPERCONDUCTING INTERCONNECT IN SILICON
A microelectromechanical system (MEMS) device and method of fabrication are provided. The MEMS devices includes a silicon substrate. The silicon substrate includes a top surface. An interconnect is machined from the silicon substrate. The interconnect includes at a spring body that has least two spring arms. Each spring arm includes a first end distal from a center of the interconnect, a second end proximate the center of the interconnect, and a single turn of a constant curvature. Each spring arm is configured to move rotationally in a plane parallel to the top surface of the silicon substrate.
Microwave detector
A system for detecting microwave power. In some embodiments, the system includes: a first resonator including a graphene-insulating-superconducting junction; a probe signal source, coupled to the first resonator; and a probe signal analyzer. The probe signal analyzer is configured: to measure a change in amplitude or phase of a probe signal received by the probe signal analyzer from the probe signal source, and to infer, from the change in amplitude or phase, a change in microwave power received by the graphene-insulating-superconducting junction.
REDUCING PARASITIC CAPACITANCE AND COUPLING TO INDUCTIVE COUPLER MODES
A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
Magnetic field measuring element, magnetic field measuring device, and magnetic field measuring system
A magnetic field measuring element includes a Superconducting QUantum Interference Device magnetic sensors, the first sensor disposed either on a second plane perpendicular to a first plane including a coil surface of the third sensor and which includes the center of the third sensor, or in the vicinity of the second plane, and a second sensor disposed either on a third plane perpendicular to the first plane and the second plane, or in the vicinity of the third plane. The center of the first sensor is present either on a straight line which passes through the center of the third sensor and is perpendicular to the first plane, or in the vicinity of said straight line, and the center of the second sensor is present in a position displaced from a line joining the center of the third sensor and the center of the first sensor.
Reducing parasitic capacitance and coupling to inductive coupler modes
A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.
LOW-POWER BIASING NETWORKS FOR SUPERCONDUCTING INTEGRATED CIRCUITS
A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.
CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR QUANTUM ANNEALING PROCESSES
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.