Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.

According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.

A device comprises first and second superconducting quantum bits, and a multimode coupler circuit coupled between the first and second superconducting quantum bits. The multimode coupler circuit comprises a first mode and a second mode, and is configured to operate in one of a first state and a second state, in response to a flux tuning control signal. In the first state, the first superconducting quantum bit is exchange coupled to the first mode, and the second superconducting quantum bit is exchange coupled to the second mode, to suppress interaction between the first and second superconducting quantum bits. In the second state, the first and second superconducting quantum bits are exchange coupled to both the first and second modes, to enable an interaction between the first and second superconducting quantum bits and perform an entanglement gate operation.

A magnetic field measuring element includes a Superconducting QUantum Interference Device magnetic sensors, the first sensor disposed either on a second plane perpendicular to a first plane including a coil surface of the third sensor and which includes the center of the third sensor, or in the vicinity of the second plane, and a second sensor disposed either on a third plane perpendicular to the first plane and the second plane, or in the vicinity of the third plane. The center of the first sensor is present either on a straight line which passes through the center of the third sensor and is perpendicular to the first plane, or in the vicinity of said straight line, and the center of the second sensor is present in a position displaced from a line joining the center of the third sensor and the center of the first sensor.

A nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer is on the substrate and includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure.

A semiconductor-superconductor hybrid structure includes a semiconductor layer and a superconductor heterostructure on the semiconductor layer. The superconductor heterostructure includes a first superconductor layer on the semiconductor layer and a second superconductor layer on the first superconductor layer. The first superconductor layer comprises a first superconducting material and the second superconductor layer comprises a second superconducting material that is different from the first superconducting material. By providing the superconductor heterostructure as multiple layers of different superconducting materials, the superconducting and physical properties of the superconductor heterostructure can be improved compared to conventional superconducting homostructures, thereby increasing the performance of the semiconductor-superconductor hybrid structure.

Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility.

A method of fabricating a semiconductor-superconductor hybrid device comprises providing a workpiece comprising a semiconductor component, a layer of a first superconductor material on the semiconductor component, and a layer of a second superconductor material on the first superconductor material, the second superconductor material being different from the first superconductor material; etching the layer of the second superconductor material to expose a portion of the first superconductor material; and oxidising the portion of the first superconductor material to form a passivating layer on the semiconductor. The first superconductor provides energy coupling between the semiconductor and the second superconductor, and the passivating layer protects the semiconductor while allowing electrostatic access thereto. Also provided are a hybrid device, and a method of etching.