A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

The present invention relates to a phononic-isolated Kinetic Inductance Detector (KID) and a method of fabrication thereof. The KID is a highly sensitive superconducting cryogenic detector which can be scaled to very large format arrays. The fabrication process of the KID of the present invention integrates a phononic crystal into a KID architecture. The phononic structures are designed to reduce the loss of recombination and athermal phonons, resulting in lower noise and higher sensitivity detectors.

A superconductor junction includes a normal metal layer having a first side and a second side, an insulating layer overlying the second side of the normal metal layer, and a first superconductor layer formed of a first superconductor material that overlies a side of the insulating layer opposite the side that overlies the normal metal layer. The superconductor junction further includes a second superconductor layer formed of a second superconductor material with a first side overlying a side of the first superconductor material opposite the side that overlies the insulating layer. The second superconductor material has a higher diffusion coefficent than the first superconductor material and/or the second superconductor material has a lower recombination coefficent than the first superconductor metal layer. A normal metal layer quasiparticle trap is coupled to a second side of the second superconductor layer.

Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.

A superconductor thermal filter is disclosed that includes a normal metal layer having a first side, an insulating layer overlying the first side of the normal metal layer, and a multilayer superconductor structure having a first side overlying a side of the insulating layer opposite the side that overlies the normal metal layer. The multilayer superconductor structure is comprised of a plurality of superconductor layers with each superconductor layer having a smaller superconducting energy band gap than the preceding superconductor as the superconductor layers extend away from the normal metal layer. The thermal filter further includes a normal metal layer quasiparticle trap having a first side and a second side with the first side being disposed on a second side of the multilayer superconductor. A bias voltage is applied between the normal metal layer and the normal metal layer quasiparticle trap to remove hot electrons from the normal metal layer.

According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure.

A quantum bit circuit includes a first Majorana carrier that includes a first edge and extends in a first direction and a second Majorana carrier that includes a second edge and extends in a second direction intersecting with the first direction, in which the first Majorana carrier includes a first region where a Majorana particle can exist, in a portion of the first edge overlapping the second edge in plan view, the second Majorana carrier includes a second region where a Majorana particle can exist, in a portion of the second edge overlapping the first edge in plan view, and the Majorana particle in the first region and the Majorana particle in the second region are exchangeable.

A superconductor device includes a substrate. There is a first silicide and a second silicide located on opposite sides of a silicon channel and on top of the substrate. A first superconducting contact is in contact with the first silicide. A second superconducting contact is in contact with the second silicide. A dielectric is located between the first and second superconducting contacts. A gate is on top of the gate dielectric.

Technologies for scalable spin qubit readout are disclosed. In the illustrative embodiment, superconducting and semiconducting components are integrated onto a single chip, allowing for frequency and temporal multiplexing components to be integrated onto the same die. The semiconducting components on the die can include transistors, varactors, and amplifiers, and the superconducting components can include an inductor and a capacitor that form part of an impedance matching network.