Described herein are devices incorporating plasmon Casimir cavities, which modify the distribution of allowable plasmon modes within the cavities. The plasmon Casimir cavities can drive charge carriers from or to an electronic device adjoining the plasmon Casimir cavity by modifying the distribution of zero-point energy-driven plasmons on one side of the electronic device to be different from the distribution of zero-point energy-driven plasmons on the other side of the electronic device. The electronic device can exhibit a structure that permits transport or capture of carriers in very short time intervals, such as in 1 picosecond or less.

A set of superconducting devices is interconnected in a lattice that is fabricated in a single two-dimensional plane of fabrication such that a superconducting connection can only reach a first superconducting device in the set while remaining in the plane by crossing a component of a second superconducting device that is also located in the plane. A superconducting coupling device having a span and a clearance height is formed in the superconducting connection of the first superconducting device. A section of the superconducting coupling device is separated from the component of the second superconducting device by the clearance in a parallel plane. A potential of a first ground plane on a first side of the component is equalized with a second ground plane on a second side of the component using the superconducting coupling device.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

A superconductivity stabilizing material used for a superconducting wire and which is formed of a copper material containing at least one of additive elements selected from Ca, Sr, Ba, and rare earth elements in a range of 3 ppm by mass or more and 100 ppm by mass or less in total, with a remainder being Cu and unavoidable impurities, in which the total concentration of the unavoidable impurities, excluding O, H, C, N, and S which are gas components, is 5 ppm by mass or more and 100 ppm by mass or less, the half-softening temperature thereof is 200 C. or lower, the Vickers hardness thereof is 55 Hv or more, and the residual resistance ratio (RRR) thereof is 50 or more and 500 or less.

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

Methods and apparatus are disclosed for cooling superconducting signal lines disposed on an interconnect such as a flexible cable or a rigid substrate. The superconducting signal lines are cooled to a cryogenic temperature lower than the temperature at which at least some superconducting logic devices coupled to the interconnect are operated. In some examples, an airtight conduit, heat pipe, or thermally conduct of strap provided to cool the superconducting interconnect. In one example of the disclosed technology, a system includes at least two sets of superconducting logic devices, cooling apparatus adapted to cool the logic devices to a first operating temperature, and interconnect coupling the superconducting logic devices, and a cooling apparatus in thermal communication with the interconnect. The apparatus is adapted to cool superconducting signal lines on the interconnect to a lower operating temperature than the first operating temperature at which the superconducting logic devices operate.

An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.

In various embodiments, superconducting wires incorporate diffusion barriers composed of Ta alloys that resist internal diffusion and provide superior mechanical strength to the wires.