H10N60/20

Integrating circuit elements in a stacked quantum computing device
11436516 · 2022-09-06 · ·

A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.

Quantum plasmon fluctuation devices

Described herein are devices incorporating plasmon Casimir cavities, which modify the distribution of allowable plasmon modes within the cavities. The plasmon Casimir cavities can drive charge carriers from or to an electronic device adjoining the plasmon Casimir cavity by modifying the distribution of zero-point energy-driven plasmons on one side of the electronic device to be different from the distribution of zero-point energy-driven plasmons on the other side of the electronic device. The electronic device can exhibit a structure that permits transport or capture of carriers in very short time intervals, such as in 1 picosecond or less.

Fabrication of reinforced superconducting wires

In various embodiments, superconducting wires feature assemblies of clad composite filaments and/or stabilized composite filaments embedded within a wire matrix. The wires may include one or more stabilizing elements for improved mechanical properties.

Magnetic resonance scanner with embedded quantum computer
11385308 · 2022-07-12 · ·

The present disclosure relates to a magnetic resonance (MR) scanner and magnetic resonance imaging (MRI) system. The MR scanner includes a superconducting magnet, a superconducting quantum processor, a first cooling system surrounding the superconducting magnet, and a second cooling system surrounding the superconducting quantum processor. The second cooling system is embedded in the first cooling system.

Superconductor ground plane patterning geometries that attract magnetic flux

Superconducting integrated circuit layouts are proofed against the detrimental effects of stray flux by designing and fabricating them to have one or more ground planes patterned in the x-y plane with a regular grid of low-aspect-ratio flux-trapping voids. The ground plane(s) can be globally patterned with such voids and thousands or more superconducting circuit devices and wires can thereafter be laid out so as not to intersect or come so close to the voids that the trapped flux would induce supercurrents in them, thus preventing undesirable coupling of flux into circuit elements. Sandwiching a wire layer between patterned ground planes permits wires to be laid out even closer to the voids. Voids of successively smaller maximum dimension can be concentrically stacked in pyramidal fashion in multiple ground plane layers having different superconductor transition temperatures, increasing the x-y area available for device placement and wire-up.

Photonic Quantum Networking for Large Superconducting Qubit Modules

In a general aspect, a photonic quantum network is disclosed. In some implementations, microwave modes and optical modes are generated on first and second quantum processing units (QPUs) by operation of a first transducer device of the first QPU and a second transducer device of the second QPU. The microwave modes are transmitted within the first and second QPUs from the first and second transducer devices to respective first and second qubit devices. The optical modes are transmitted from the first and second QPUs to an interferometer device. By operation of the interferometer device, output signals are generated on respective output channels based on the optical modes from the first and second QPUs. Based on the output signals detected by operation of photodetector devices coupled to the respective output channels, quantum entanglement transferred to the first and second qubit devices by the microwave modes is identified.

METHOD AND SYSTEM FOR GENERATING AND REGULATING LOCAL MAGNETIC FIELD VARIATIONS FOR SPIN QUBIT MANIPULATION USING MICRO-STRUCTURES IN INTEGRATED CIRCUITS

The embodiments herein provide a method and a system for generating and regulating local magnetic field variations required for spin qubit manipulation based on scalable quantum processors using micro-structures in integrated circuits. In an embodiment the system provides an adaptive and independent magnetic-field control to each qubit on a hardware substrate and comprises several micro/nano-scale current-carrying structures near a qubit for controlling and manipulating the qubit using the locally generated variable magnetic field, in-turn controlled by the tunable current flowing through these structures. The current-carrying structures in conjunction with fast current control provides fast switching/tuning of magnetic fields for rapid adiabatic passage control of one or more qubits simultaneously. The tenability of the qubits allows post-fabrication setting of adaptive magnetic field strengths and frequency separation of qubits thereby enabling the qubits to simultaneously realize their intended control signals without any added disturbance from neighboring qubits.

Phononic devices and methods of manufacturing thereof

The present invention relates to a plurality of phononic devices and a method of manufacturing thereof. In one embodiment, highly sensitive superconducting cryogenic detectors integrate phononic crystals into their architecture. The phononic structures are designed to reduce the loss of athermal phonons, resulting in lower noise and higher sensitivity detectors. This fabrication process increases the qp generation recombination rate, thus, reducing the noise equivalent power (NEP) without sacrificing the scalability. A plurality of phononic devices, such as a kinetic inductance detector (KID), a transition edge sensor (TES) bolometer, and quarterwave backshort, can be manufactured according to the methods of the present invention.

COMPOUND SUPERCONDUCTING TWISTED WIRE AND REWINDING METHOD FOR COMPOUND SUPERCONDUCTING TWISTED WIRE

The present invention provides: a compound superconducting twisted wire in which non-adhesiveness between compound superconducting strands or separation easiness after adhesion is improved while a strength against tension is improved to a degree to be equivalent to or stronger than that of a conventional compound superconducting twisted wire; and a rewinding method thereof. The compound superconducting twisted wire 1 of the present invention includes a plurality of compound superconducting strands 10 being twisted to form a twisted structure, in which each of the compound superconducting strands 10 includes a compound superconductor part 11, a reinforcing part 12 and a stabilizing part 13, in which the compound superconductor part 11 includes a plurality of compound superconducting filaments 15 and a first matrix 16, the compound superconducting filaments 15 each including a compound superconducting phase, in which the reinforcing part 12 is disposed on an outer circumferential side of the compound superconductor part, and comprises a plurality of reinforcing filaments 18 and a second matrix 19, in which the stabilizing part 13 is disposed on at least one side of an inner circumferential side and an outer circumferential side of the reinforcing part. In the compound superconducting twisted wire, a volume ratio of the reinforcing part relative to the compound superconducting strand is larger than a volume ratio of the compound superconductor part relative to the compound superconducting strand, or a metal layer 20 with a thickness of 2 μm or less is formed on a surface of the compound superconducting strand for preventing thermal fusion between the compound superconducting strands.

Enhanced superconducting transition temperature in electroplated Rhenium

This disclosure describes systems, methods, and apparatus for multilayer superconducting structures comprising electroplated Rhenium, where the Rhenium operates in a superconducting regime at or above 4.2 K, or above 1.8 K where specific temperatures and times of annealing have occurred. The structure can include at least a first conductive layer applied to a substrate, where the Rhenium layer is electroplated to the first layer. A third layer formed from the same or a different conductor as the first layer can be formed atop the Rhenium layer.