The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

A transistor includes (i) a first wire including a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature and (ii) a second wire including a superconducting component configured to operate in a superconducting state while: a temperature of the superconducting component is below a superconducting threshold temperature and a first input current supplied to the superconducting component is below a current threshold. The semiconducting component is located adjacent to the superconducting component. In response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first input current exceeds the lowered current threshold.

The various embodiments described herein include methods, devices, and systems for fabricating and operating diodes. In one aspect, an electrical circuit includes: (1) a diode component having a particular energy band gap; (2) an electrical source electrically coupled to the diode component and configured to bias the diode component in a particular state; and (3) a heating component thermally coupled to a junction of the diode component and configured to selectively supply heat corresponding to the particular energy band gap.

Self-powered scale-up toroidal array quantum processing memory device with controllable and adjustable state-switch valves (CASSV) of making and applications at room temperature in a One-Device-Assembly was invented. The devices comprise of multiple layer organo-metallic cross-linked polymers having various superlattice structures based on a double-pole electron-relay in an electron negative and an electron positive manner in the membranes that promoted Cooper pairs coherently transmitting waves within and cross the Josephson toroidal flexible junction barriers at zero-bias. In the One-Device-Assembly system, the CASSV valve provides a delicate balance and enables the whole device system working when an fJ energy consumption was in demand from the quantum qubits; or when an energy storage device stores 1.53 MJ/cm.sup.2 in demand for a routine automobile vehicle without energy dissipation.

Embodiments of a Majorana-based qubit are disclosed herein. The qubit is based on the formation of superconducting islands, some parts of which are topological (T) and some parts of which are non-topological. Also disclosed are example techniques for fabricating such qubits. In one embodiment, a semiconductor nanowire is grown, the semiconductor nanowire having a surface with an oxide layer. A dielectric insulator layer is deposited onto a portion of the oxide layer of the semiconductor nanowire, the portion being designed to operate as a non-topological segment in the quantum device. An etching process is performed on the oxide layer of the semiconductor nanowire that removes the oxide layer at the surface of the semiconductor nanowire but maintains the oxide layer in the portion having the deposited dielectric insulator layer. A superconductive layer is deposited on the surface of the semiconductor nanowire, including over the dielectric insulator layer.

According to an example aspect of the present invention, there is provided an apparatus comprising: an optic fibre input (31); a plurality of photonic detectors (34) comprising a nanowire and biased with an electric input; a set of modulators (35) connected to the optic fibre input (31), each of the modulators (35) being connected to one of the photonic detectors (34) for forming a modulated optical detector signal; and an optic fibre output (40) for the modulated optical detector signal. The optic fibre input (31), the photonic detectors (34), the set of modulators (35), and the optic fibre output (40) are formed on a single chip (1).

The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a superconducting component includes: (1) a superconductor having a plurality of alternating narrow and wide portions, each wide portion having a corresponding terminal; and (2) a plurality of heat sources, each heat source thermally coupled to a corresponding narrow portion such that heat from the heat source is transmitted to the corresponding narrow portion; where the plurality of heat sources is electrically isolated from the superconductor.

Provided is a superconducting coil having a spiral structure for a current limiter. The coil includes: a first superconducting tape, a second superconducting tape, and an insulating isolation layer, where the first superconducting tape and the second superconducting tape have spiral structures, an end of the first superconducting tape at a spiral center is connected to an end of the second superconducting tape at the spiral center, the instating isolation laser is filled between the first superconducting tape and the second superconducting tape, and a spacing between the first superconducting tape and the second superconducting tape gradually increases from the spiral center to an outer spiral periphery.

Provided are a method and apparatus for calculating fault resistance and a current-limiting current of a superconducting fault current limiter. The method includes: calculating a first short-circuit fault current I.sub.n(t) of a power grid short-circuit fault transient circuit calling an external characteristic model U(I, t), and calculating resistance R.sub.n(t) of a superconducting fault current limiter under the first short-circuit fault current I.sub.n(t); adding the resistance R.sub.n(t) of the superconducting fault current limiter into the power grid short-circuit fault transient circuit, and calculating a second short-circuit fault current I.sub.m(t), where m=n+1; and determining whether an error between the second short-circuit fault current I.sub.m(t) and the first short-circuit fault current I.sub.n(t) is smaller than a preset threshold value, if yes, determining the fault resistance and the current-limiting current of the superconducting fault current limiter to be R.sub.n(t) and I.sub.m(t) respectively; otherwise I.sub.n(t)=I.sub.m(t), returning for iteration.