Josephson junctions are the main circuit element of superconducting quantum information devices due to their nonlinear inductance properties and fabrication scalability. However, large scale integration necessarily depends on high fidelity and high yielding fabrication of Josephson junctions. The standard Josephson junction technique depends on a submicron suspended resist Dolan bridge that tends to be very fragile and fractures during the fabrication process. The present invention is directed to a new tunnel junction resist mask that incorporates stress-relief channels to reduce the intrinsic stress of the resist, thereby increasing the survivability of the Dolan bridge during device processing, resulting in higher Josephson junction yield.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.

A superconducting complex quantum computing circuit includes a circuit substrate in which a wiring pattern of a circuit element including quantum bits and measurement electrodes, and ground patterns are formed, and through-electrodes connecting the ground pattern formed on a first surface of the substrate surface and the ground pattern formed on a second surface; a first ground electrode including a first contact portion in contact with the ground patterns, and a first non-contact portion having a shape corresponding to a shape of the wiring pattern; a second ground electrode including a second contact portion in contact with the ground pattern; a control signal line provided with a contact spring pin at a tip; and a pressing member that presses the first ground electrode against the first surface of the circuit substrate or presses the second ground electrode against the second surface of the circuit substrate.

An interconnection for flex circuit boards used, for instance, in a quantum computing system are provided. In one example, the interconnection can include a first flex circuit board having a first side and a second side opposite the first side. The interconnection can include a second flex circuit board having a third side and a fourth side opposite the third side. The first flex circuit board and the second flex circuit board are physically coupled together in an overlap joint in which a portion of the second side for the first flex circuit board overlaps a portion of the third side of the flex circuit board. The interconnection can include a signal pad structure positioned in the overlap joint that electrically couples a first via in the first flex circuit board and a second via in the second flex circuit board.

Apparatus, methods, and systems are disclosed for robust scalable topological quantum computing. Quantum dots are fabricated as van der Waals heterostructures, supporting localized topological phases and non-Abelian anyons (quasiparticles). Large bandgaps provide noise immunity. Three-dot structures include an intermediate quantum dot between two computational quantum dots. With the intermediate quantum dot in an OFF state, quasiparticles at the computational quantum dots can be isolated, with long lifetimes. Alternatively, the intermediate quantum dot can be controlled to decrease the quasiparticle tunneling barrier, enabling fast computing operations. A computationally universal suite of operations includes quasiparticle initialization, braiding, fusion, and readout of fused quasiparticle states, with, optionally, transport or tunable interactions—all topologically protected. Robust qubits can be operated without error correction. Quasilinear arrays of quantum dots or qubits can be scaled arbitrarily, up to resource limits, and large-scale topological quantum computers can be realized. Extensive two-dimensional arrays can also be used.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

Operational characteristics of an high temperature superconducting (“HTS”) film comprised of an HTS material may be improved by depositing a modifying material onto appropriate surfaces of the HTS film to create a modified HTS film. In some implementations of the invention, the HTS film may be in the form of a “c-film.” In some implementations of the invention, the HTS film may be in the form of an “a-b film,” an “a-film” or a “b-film.” The modified HTS film has improved operational characteristics over the HTS film alone or without the modifying material. Such operational characteristics may include operating in a superconducting state at increased temperatures, carrying additional electrical charge, operating with improved magnetic properties, operating with improved mechanic properties or other improved operational characteristics. In some implementations of the invention, the HTS material is a mixed-valence copper-oxide perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.

A memory cell having a Josephson junction and a magnetic junction situated in a close proximity to the Josephson junction. The two junctions may be vertically integrated. The magnetic junction has at least two magnetic layers with different coercive forces and a non-magnetic layer therebetween, to form a spin valve or pseudo-spin valve. A magnetization direction of a magnetic layer with lower coercive force can be rotated with respect to the larger coercive force magnetic layer(s). Magnetic fields produced by appropriately configured control lines carrying electric current, or spin-polarized current through the magnetic junction, can result in rotation. The magnetic junction influences the Josephson critical current of the Josephson junction, leading to distinct values of critical current which can serve as digital logic states. The so obtained memory cell can be integrated into the large arrays containing a plurality of the cells, to enable the selective READ and WRITE operations.

Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.