H10N60/80

Antenna-based qubit annealing method

Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.

Quantum device with modular quantum building blocks

Techniques for a quantum device with modular quantum building blocks are provided. In one embodiment, a device is provided that comprises a substrate that is coupled with a plurality of qubit pockets, where at least one qubit pocket of the plurality of qubit pockets is coupled with a qubit. In one implementation, the device can further comprise a plurality of connectors coupled to the substrate and positioned around at least a portion of the substrate, where the plurality of connectors comprising a connecting element. In one or more implementations, the device can further comprise a plurality of transmission lines formed on the substrate and connect at least one connector of the plurality of connectors to at least one qubit pocket of the plurality of qubit pockets.

QUANTUM PROCESSING UNIT COMPRISING ONE OR MORE SUPERCONDUCTING QUBITS BASED ON PHASE-BIASED LINEAR AND NON-LINEAR INDUCTIVE-ENERGY ELEMENTS
20230371404 · 2023-11-16 ·

A quantum processing unit is disclosed. The quantum processing unit includes at least one superconducting qubit based on phase-biased linear and non-linear inductive-energy elements. A superconducting phase difference across the linear and non-linear inductive-energy elements is biased, for example, by an external magnetic field, such that quadratic potential energy terms of the linear and non-linear inductive-energy elements are cancelled at least partly. In a preferred embodiment, such cancellation is at least 30%. The partial cancellation of the quadratic potential makes it possible to implement a high-coherence high-anharmonicity superconducting qubit design.

Quantum computing device and system

Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib

Topologies for interconnecting capacitive and inductive elements in a capacitively-coupled rib are described. An example relates to a resonant clock network (RCN) that resonates in response to both a first clock signal having a first phase and a second clock signal having a second phase. The RCN includes at least one rib coupled to at least one spine. The rib includes a first capacitive line configured to receive the first clock signal and provide, via a first capacitor, a first bias current to a first superconducting circuit. The rib further includes a second capacitive line configured to receive the second clock signal and provide, via a second capacitor, a second bias current to a second superconducting circuit. The rib further includes at least one inductive line configured to connect the first capacitive line with the second capacitive line forming a direct connection between the two capacitive lines.

SUPERCONDUCTING QUANTUM CIRCUIT APPARATUS
20230363293 · 2023-11-09 · ·

A superconducting quantum circuit apparatus includes a resonator including a SQUID including at least two Josephson junctions in a loop, a magnetic field application part that includes a conductor portion, a current passing therethrough generating a magnetic flux penetrating through the SQUID, the current supplied from a current control part, and a parallel LC circuit including an inductor and a capacitor each made of a superconducting material, the inductor and the capacitor having respective one ends connected in common to the magnetic field application part and respective other ends connected in common to a current path from the current control part.

MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY

Devices and methods that facilitate modular quantum systems with discreet levels of connectivity are provided. In various embodiments, a quantum computing device can comprise one or more modules comprising at least qubits, buses, and readout structures; a plurality of couplers, wherein the plurality of couplers comprises at least two couplers selected from a group consisting of: classical couplers, short-range couplers, and long-range couplers, that are adapted for coupling a plurality of the at least qubits, buses, and readout structures; and a connection from the one or more modules to one or more classical controllers external to a cryogenic environment comprising the one or more modules.

MODULAR QUANTUM SYSTEM WITH DISCRETE LEVELS OF CONNECTIVITY

Devices and methods that facilitate modular quantum systems with discreet levels of connectivity are provided. In various embodiments, a quantum computing device can comprise one or more modules comprising at least qubits, buses, and readout structures; a plurality of couplers, wherein the plurality of couplers comprises at least two couplers selected from a group consisting of: classical couplers, short-range couplers, and long-range couplers, that are adapted for coupling a plurality of the at least qubits, buses, and readout structures; and a connection from the one or more modules to one or more classical controllers external to a cryogenic environment comprising the one or more modules.

Quantum device

A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

QUANTUM CHIP TEST STRUCTURE AND FABRICATION METHOD THEREFOR, AND TEST METHOD AND FABRICATION METHOD FOR QUANTUM CHIP

Disclosed are a quantum chip test structure and a fabrication method therefor, and a test method and a fabrication method for a quantum chip. The quantum chip test structure includes: a superconducting Josephson junction and a connection structure of the superconducting Josephson junction that are located on a substrate; a first isolation layer located on the connection structure, where a connection window penetrating through the first isolation layer is formed in the first isolation layer; a second isolation layer located on the first isolation layer, where a deposition window is formed in the second isolation layer; and an electrical connection portion located in the connection window and an electrical connection layer located in the deposition window, and the electrical connection layer is configured to implement electrical contact with a test device.