A method for fabricating memory device is provided. The method includes forming a transistor on a substrate. Further, a contact structure is formed on a source/drain region of the transistor. A conductive layer is formed on the contact structure. Four memory structures are formed on the conductive layer to form a quadrilateral structure.

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

Embodiments include a resistive random access memory (RRAM) storage cell, having a resistive switching material layer and a semiconductor layer between two electrodes, where the semiconductor layer serves as an OEL. In addition, the RRAM storage cell may be coupled with a transistor to form a RRAM memory cell. The RRAM memory cell may include a semiconductor layer as a channel for the transistor, and also shared with the storage cell as an OEL for the storage cell. A shared electrode may serve as a source electrode of the transistor and an electrode of the storage cell. In some embodiments, a dielectric layer may be shared between the transistor and the storage cell, where the dielectric layer is a resistive switching material layer of the storage cell.

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

A memory device includes transistors and a memory cell array disposed over and electrically coupled to the transistors. The memory cell array includes word lines, bit line columns, and data storage layers interposed between the word lines and the bit line columns. A first portion of the word lines on odd-numbered tiers of the memory cell array is oriented in a first direction, and a second portion of the word lines on even-numbered tiers of the memory cell array is oriented in a second direction that is angularly offset from the first direction. The bit line columns pass through the odd-numbered tiers and the even-numbered tiers, and each of the bit line columns is encircled by one of the data storage layers. A semiconductor die and a manufacturing method of a semiconductor structure are also provided.

A resistive memory device and a method of manufacturing the same are disclosed. The resistive memory device includes an insulating layer disposed on a substrate and having a contact hole exposing a surface portion of the substrate, a lower electrode disposed in the contact hole, an adhesive layer disposed between the contact hole and the lower electrode, a first diffusion barrier layer disposed between the adhesive layer and the lower electrode, a second diffusion barrier layer disposed on the insulating layer, the lower electrode, the adhesive layer and the first diffusion barrier layer, a variable resistance layer disposed on the second diffusion barrier layer, and an upper electrode disposed on the variable resistance layer.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode, a second electrode, and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer comprises at least one transition metal oxide. The second electrode may include a first layer comprising a first metallic material and a second layer comprising a second metallic material. In some embodiments, the first metallic material and the second metallic material may include titanium and tantalum, respectively. In some embodiments, the second electrode may include an alloy of tantalum. The alloy of tantalum may contain one or more of hafnium, molybdenum, niobium, tungsten, and/or zirconium. In some embodiments, the alloy of tantalum contains a plurality of alloys of tantalum.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.