Methods, systems, and devices for decoding for a memory device are described. A decoder may include a first vertical n-type transistor and a second vertical n-type transistor that extends in a third direction relative to a die of a memory array. The first vertical n-type transistor may be configured to selectively couple an access line with a source node and the second n-type transistor may be configured to selectively couple the access line with a ground node. To activate the access line coupled with the first and second vertical n-type transistors, the first vertical n-type transistor may be activated, the second vertical n-type transistor may be deactivated, and the source node coupled with the first vertical n-type transistor may have a voltage applied that differs from a ground voltage.

A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.

A resistive memory device is provided. The resistive memory device comprises a first electrode and a resistive layer over the first electrode, the resistive layer having a sidewall. A second electrode is over the resistive layer. An insulating liner is formed on the sidewall of the resistive layer. The insulating liner comprises two layers of different dielectric materials.

A method of producing a recurrent neural network computer includes consecutive steps of providing a substrate with a first electrode; structuring the first electrode by etching using a first mask made of block copolymers, such that said electrode has free regions which are randomly spatially distributed; forming a resistive-RAM-type memory layer on the first structured electrode; forming a second electrode on the memory layer; and structuring the second electrode by etching, using a second mask made of block copolymers such that said electrode has free regions which are randomly spatially distributed.

Technologies for reducing series resistance are disclosed. An example method may include: forming a first layer on a temporary substrate; forming a second layer on the first layer; etching the first layer and the second layer to form a trench; electroplating a top electrode via the trench, wherein the top electrode partially formed on a top surface of the second layer; removing the first layer and the second layer; forming a curable layer on the temporary substrate and the top electrode; removing the temporary substrate from the curable layer and the top electrode; forming a cross-point device on the curable layer and the top electrode; forming a bottom electrode on the cross-point device; and forming a flexible substrate on the bottom electrode.

A method for manufacturing a semiconductor device includes forming a plurality of memory elements on a first interconnect level, and forming an etch stop layer on the plurality of memory elements. A dielectric layer is formed on the etch stop layer, and a portion of the dielectric over the plurality of memory elements is removed to expose a portion of the etch stop layer. The method further includes removing the exposed portion of the etch stop layer. The removing of the portion of the dielectric layer and of the exposed portion of the etch stop layer forms a trench. A metallization layer is formed in the trench on the plurality of memory elements, wherein the metallization layer is part of a second interconnect level.

A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

Embodiments disclosed herein include an RRAM cell. The RRAM cell may include a first nanowire electrically connected to a first wordline electrode. The nanowire may include a first sharpened point distal from the first wordline electrode. The RRAM cell may also include a metal contact electrically connected to a bitline electrode and a high-κ dielectric layer directly between the nanowire and the metal contact.

A memory device is provided that includes a method and structure for forming a resistive memory (RRAM) which has a gradual instead of abrupt change of resistance during programming, rendering it suitable for analog computing. In a first embodiment: One electrode of the inventive RRAM comprises a metal-nitride material (e.g., titanium nitride (TiN)) with gradually changing concentration of a metal composition (e.g., titanium). Different Ti concentrations in the electrode results in different concentration of oxygen vacancy in the corresponding section of the RRAM thereby exhibiting a gradual change of resistance dependent upon an applied voltage. The total conductance of the RRAM is the sum of conductance of each section of the RRAM. In a second embodiment: a RRAM with one electrode having multiple forks of electrodes with different composition concentration and thus different switching behaviors, rendering the inventive RRAM changing conductance gradually instead of abruptly.

A resistive random access memory cell includes a first electrode layer, an oxygen reservoir layer, a variable resistance layer, and a second electrode. The first electrode layer is located on a dielectric layer, and includes a body part extending in a first direction and multiple extension parts connected to a sidewall of the body part and extending in a second direction. The second direction is perpendicular to the first direction. The oxygen reservoir layer covers the first electrode layer. The variable resistance layer is located between the first electrode layer and the oxygen reservoir layer. The second electrode is located above a top surface of the oxygen reservoir layer and around an upper sidewall of the oxygen reservoir layer.