A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

A resistive random access memory (RRAM) device and a manufacturing method are provided. The RRAM device includes bottom electrodes, a resistance switching layer, insulating patterns, a channel layer and top electrodes. The resistance switching layer blanketly covers the bottom electrodes. The insulating patterns are disposed on the resistance layer and located in corresponding to locations of the bottom electrodes. The channel layer conformally covers the resistance switching layer and the insulating patterns. The channel layer has a plurality of channel regions. The channel regions are located on the resistance switching layer, and cover sidewalls of the insulating patterns. The top electrodes respectively cover at least two of the channel regions, and respectively located in corresponding to one of the insulating patterns, such that the at least two of the channel regions are located between one of the bottom electrodes and one of the top electrodes.

A variable resistance memory device and a method of fabricating a variable resistance memory device, the device including first conductive lines extending in a first direction; second conductive lines extending in a second direction crossing the first direction; and memory cells at respective intersection points of the first conductive lines and the second conductive lines, wherein each of the memory cells includes a switching pattern, an intermediate electrode, a variable resistance pattern, and an upper electrode, which are between the first and second conductive lines and are connected in series; and a spacer structure including a first spacer and a second spacer, the first spacer being on a side surface of the upper electrode, and the second spacer covering the first spacer and a side surface of the variable resistance pattern such that the second spacer is in contact with the side surface of the variable resistance pattern.

A memory device includes a bottom electrode, a selector, a memory layer, and a top electrode. The selector is over the bottom electrode. A sidewall of the bottom electrode and a sidewall of the selector are coterminous. The memory layer is formed over the selector and has a width greater than a width of the selector. A top electrode is formed over the memory layer.

The present disclosure, in some embodiments, relates to a method of forming a memory device. The method includes forming a data storage layer on a bottom electrode layer over a substrate, forming a first top electrode layer over the data storage layer, and forming a second top electrode layer over the first top electrode layer. The first top electrode layer has a smaller corrosion potential than the second top electrode layer. A first patterning process is performed on the first top electrode layer and the second top electrode layer to define a multi-layer top electrode. A second patterning process is performed on the data storage layer and the bottom electrode layer to define a data storage structure and a bottom electrode.

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

A manufacturing method is provided. The method includes steps below. Forming bottom electrodes. Blanketly forming a resistance switching layer on the bottom electrodes. Forming a first insulating material layer on the resistance switching layer. Patterning the first insulating material layer to form insulating patterns. Conformally forming a channel layer having a plurality of channel regions on the resistance switching layer and the insulating patterns, wherein the plurality of channel regions are located on the resistance switching layer and cover opposite sides of the insulating patterns. Forming a second electrode material layer on the channel layer. Patterning the second electrode material layer to form top electrodes, each of the top electrodes is located in corresponding to one of the insulating patterns and covers at least two of the plurality of channel regions.

A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.