The performance of a ReRAM structure may be stabilized by utilizing a dry chemical gas removal (or cleaning) process to remove sidewall residue and/or etch by-products after etching the ReRAM stack layers. The dry chemical gas removal process decreases undesirable changes in the ReRAM forming voltage that may result from such sidewall residue and/or etch by-products. Specifically, the dry chemical gas removal process may reduce the ReRAM forming voltage that may otherwise result in a ReRAM structure that has the sidewall residue and/or etch by-products. In one embodiment, the dry chemical gas removal process may comprise utilizing a combination of HF and NH.sub.3 gases. The dry chemical gas removal process utilizing HF and NH.sub.3 gases may be particularly suited for removing halogen containing sidewall residue and/or etch by-products.

A memory device may be provided, including a substrate; one or more bottom electrodes arranged over the substrate; one or more switching layers arranged over the one or more bottom electrodes; and a plurality of top electrodes arranged over the one or more switching layers. Each of the one or more bottom electrodes may include at least one corner tip facing the switching layer, and an angle of each of the at least one corner tip may be less than ninety degrees.

An resistive random-access memory (RRAM) device including an first crystalline semiconductor layer disposed adjacent to a crystalline semiconductor substrate, a crystal lattice edge-dislocation segment disposed at an interface of the first crystalline semiconductor layer and crystalline semiconductor substrate, the lattice edge-dislocation segment including first and second segment ends, a first ion-source electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the first segment end of the lattice edge-dislocation segment, and a second electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the second segment end of the lattice edge-dislocation segment.

A memristive device is described. The memristive device includes a first layer having a first plurality of conductive lines, a second layer having a second plurality of conductive lines, and memristive interlayer connectors. The first and second layers differ. The first and second pluralities of conductive lines are each lithographically defined. The first and second pluralities of conductive lines are insulated from each other. The memristive interlayer connectors are memristively coupled with a first portion of the first plurality of conductive lines and memristively coupled with a second portion of the second plurality of conductive lines. The memristive interlayer connectors are thus sparsely coupled with the first and second pluralities of conductive lines. Each memristive interlayer connector includes a conductive portion and a memristive portion. The memristive portion is between the conductive portion and corresponding line(s) of the first plurality of conductive lines and/or the second plurality of conductive lines.

Methods, systems, and devices for decoding architecture for memory tiles are described. Word line tiles of a memory array may each include multiple word line plates, which may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. A pillar tile may include one or more pillars that extend vertically between the word line plate fingers. Memory cells may each be couple with a respective word line plate finger and a respective pillar. Word line decoding circuitry, pillar decoding circuitry, or both, may be located beneath the memory array and in some cases may be shared between adjacent pillar tiles.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

A method includes providing a substrate having a main surface, forming a layer of thermally insulating material on the main surface, forming strips of phase change material on the layer of thermally insulating material such that strips of phase change material are separated from the main surface by thermally insulating material, forming first and second RF terminals on the main surface that are laterally spaced apart from one another and connected to the strips of phase change material, and forming a heater structure having heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material, wherein each of the strips of phase change material includes multiple outer faces, and wherein portions of both outer faces from the strips of phase change material are disposed against one of the heating elements.

A phase-change memory device includes a bottom electrode; a stack of alternating electrical conductor layers directly contacting a top surface of the bottom electrode; a metal pillar directly contacting a top surface of the stack; a phase change material element directly contacting a top surface of the metal pillar; and a top electrode on the phase change material element, wherein a lateral dimension of the metal pillar is smaller than that of the stack.

A method for producing a resistive memory cell from a stack of layers having a metal-oxide layer interleaved between first and second electrodes includes forming, within one from among the first and second electrodes, an interlayer material-based electrode interlayer having a selectivity to etching greater than or equal to 2:1 relative to materials of the electrodes. During an etching of the stack, overetching is performed configured to laterally consume, in a horizontal direction, the interlayer material such that the electrode interlayer has a lateral recess greater than or equal to 10 nm.

The present disclosure relates to a chalcogenide material including germanium (Ge) with a first atomic percent, selenium (Se) with a second atomic percent that is at least twice the first atomic percent of the germanium, and indium (In) with a third atomic percent less the first atomic percent of the germanium.