Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. A method for fabricating a crossbar device may include forming a bottom electrode on a substrate, forming a switching oxide stack on the bottom electrode, and forming a top electrode on the switching oxide stack. Fabricating the switching oxide stack may include fabricating a plurality of base oxide layers and a plurality of discontinuous oxide layers alternately stacked, wherein the base oxide layers comprise one or more base oxides, wherein the one or more base oxides comprise at least one of TaOx, HfOx, TiOx, or ZrOx.

The present disclosure includes three dimensional memory arrays. An embodiment includes a first plurality of conductive lines separated from one another by an insulation material, a second plurality of conductive lines arranged to extend substantially perpendicular to and pass through the first plurality of conductive lines and the insulation material, and a storage element material formed between the first and second plurality of conductive lines where the second plurality of conductive lines pass through the first plurality of conductive lines. The storage element material is between and in direct contact with a first portion of each respective one of the first plurality of conductive lines and a portion of a first one of the second plurality of conductive lines, and a second portion of each respective one of the first plurality of conductive lines and a portion of a second one of the second plurality of conductive lines.

Proposed are a layered Group III-V compound having ferroelectric properties, a Group III-V compound nanosheet that may be prepared using the same, and an electrical device including the materials. Proposed is a layered compound represented by [Formula 1] M.sub.x−mA.sub.yB.sub.z (M is at least one of Group I or Group II elements, A is at least one of Group III elements, B is at least one of Group V elements, x, y, and z are positive numbers which are determined according to stoichiometric ratios to ensure charge balance when m is 0, and 0<m<x), and having ferroelectric-like properties.

A device and a method of forming the same are provided. The device includes a substrate, a first dielectric layer over the substrate, a bottom electrode extending through the first dielectric layer, a first buffer layer over the bottom electrode, a phase-change layer over the first buffer layer, a top electrode over the phase-change layer, and a second dielectric layer over the first dielectric layer. The second dielectric layer surrounds the phase-change layer and the top electrode. A width of the top electrode is greater than a width of the bottom electrode.

A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.

A semiconductor device includes a substrate, a plurality of word line structures disposed over the substrate to be spaced apart from each other in a first direction perpendicular to a surface of the substrate. Each of the plurality of word line structures extends in a second direction parallel to the surface of the substrate. In addition, the semiconductor device includes a switching layer disposed over the substrate to contact side surfaces of the plurality of word line structures, and bit line structures disposed over the substrate to extend in the first direction and to contact a surface of the switching layer. The switching layer is configured to perform a threshold switching operation, and has a variable programmable threshold voltage.

A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.

A resistive random access memory (RRAM) device includes a plurality of memory cells, each of at least a subset of the memory cells including first and second electrodes and an organic thin film compound mixed with silver perchlorate (AgClO.sub.4) salt as a base layer that is incorporated with a prescribed quantity of inorganic metal oxide molecules using vapor-phase infiltration (VPI), the base layer being formed on an upper surface of the first electrode and the second electrode being formed on an upper surface of the base layer. Resistive switching characteristics of the RRAM device are controlled as a function of a concentration of AgClO.sub.4 salt in the base layer. A variation of device switching parameters is controlled as a function of an amount of infiltrated metal oxide molecules in the base layer.

Methods, systems, and devices for fabrication of memory cells are described. An electrode layer may have an initial thickness variation after being formed. The electrode layer may be smoothened prior to forming additional layers of a memory cell, thus decreasing the thickness variation. The subsequent layer fabricated may have a thickness variation that may be dependent on the thickness variation of the electrode layer. By decreasing the thickness variation of the electrode layer prior to forming the subsequent layer, the subsequent layer may also have a decreased thickness variation. The decreased thickness variation of the subsequent layer may impact the electrical behavior of memory cells formed from the subsequent layer. In some cases, the decreased thickness variation of the subsequent layer may allow for more predictable voltage thresholds for such memory cells, thus increasing the read windows for the memory cells.

A method for manufacturing a memory resistor device. A first layer of a dielectric material is deposited onto a first electrode. A subsection of the first layer of the dielectric material is removed to expose one or more edges of the dielectric material and a second layer of the dielectric material is deposited to create one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material. A second electrode is provided, wherein the one or more boundaries between the one or more edges of the first layer of the dielectric material and the second layer of the dielectric material extend at least partially from the first electrode to the second electrode.