A tunable nonvolatile resistive element, wherein the device conductance is modulated by changing the length of a contact between a phase change material and a resistive liner. By choosing the contact length to be less than the transfer length a linear modulation of the conductance is obtained.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

In a method for using or forming a semiconductor structure. The semiconductor structure may include a resistive random access memory (RRAM) gate with a first electrode and a second electrode. The RRAM gate may also include a switching layer that includes a dielectric material having a switching layer k-value and a switching layer thermal conductivity. The RRAM gate may also include a complimentary switching (CS) mitigation layer with a material having a CS k-value that is lower than the switching layer k-value and a CS thermal conductivity that is higher than the switching layer thermal conductivity.

The present disclosure relates to a memory device. The memory device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes one or more metals having non-zero concentrations that change as a distance from the substrate increases.

A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The carbon-containing liner may include a carbon-doped liner, such as a carbon-doped oxide liner provided by way of atomic layer deposition of an oxide at temperatures between about 100 degrees Celsius to about 300 degree Celsius using carbon as a precursor.

A method for forming an in-situ drift-mitigation liner on a sidewall of a phase-change material (PCM) device stack includes providing an intermediate device including a substrate including a bottom wiring portion, a bottom electrode metal layer, a drift-mitigation liner layer, an active area layer, a carbon layer, a top electrode metal layer, patterning the top electrode metal layer to form a top electrode, performing a first intermediate angle ion beam etch (IBE), etching the carbon layer and the active area layer, which are formed on the drift-mitigation liner, to form a carbon portion and an active area portion of the PCM device stack, and performing a low angle IBE, etching the drift-mitigation liner and redepositing material etched from the drift-mitigation liner as a conductive liner material on sidewalls of the PCM device stack including exposed portions of the carbon portion, the active area portion, and the top electrode.

A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.

The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device includes a first electrode over a substrate and a second electrode over the substrate. A data storage structure is disposed between the first electrode and the second electrode. The data storage structure includes a first metal and a second metal. The first metal has a peak concentration at a first distance from the first electrode and the second metal has a peak concentration at a second distance from the first electrode. The first distance is different than the second distance.

A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, a storage element layer, and a protective layer. The storage element layer is disposed between the bottom and top electrodes. The protective layer covers the storage element layer and the top electrode, and a material of the protective layer is derived from the storage element layer. A semiconductor device having the memory cell is also provided.