Methods of forming a stack without damaging underlying layers are discussed. The encapsulation layer and dielectric layer are highly conformal, have low etch rates, and good hermeticity. These films may be used to protect chalcogen materials in PCRAM devices or any substrates sensitive to oxygen or moisture. Some embodiments utilize a two-step process comprising a first ALD process to form an encapsulation layer and oxidation process to form a dielectric layer.

A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance changeable layer, an oxygen reservoir layer and a reactive oxygen barrier layer. The bottom electrode is disposed on a substrate. The top electrode is disposed above the bottom electrode. The resistance changeable layer is disposed between the bottom electrode and the top electrode. The oxygen reservoir layer is disposed between the resistance changeable layer and the top electrode. The reactive oxygen barrier layer is disposed inside the oxygen reservoir layer.

Resistive memory cells are described. In some embodiments, the resistive memory cells include a switching layer having an inner region in which one or more filaments is formed. In some instances, the filaments is/are formed only within the inner region of the switching layer. Methods of making such resistive memory cells and devices including such cells are also described.

An electronic device includes a substrate, a channel portion, a first electrode, a second electrode, and a shape change generation portion. The channel portion is provided above the substrate and includes a phase transition material that undergoes a phase transition between a metal phase and an insulator phase owing to shape change. The first electrode is provided above the channel portion and electrically connected to a part of an upper surface of the channel portion. The second electrode is provided above the channel portion and electrically connected to another part of the upper surface of the channel portion. The shape change generation portion is configured to force the channel portion to cause shape change.

A semiconductor memory device according to an embodiment comprises: a semiconductor substrate which extends in first and second directions; first wiring lines which are arranged in a third direction, and which extend in the first direction; second wiring lines which are arranged in the first direction and extend in the third direction; and memory cells disposed at intersections of the first wiring lines and the second wiring lines, one of the memory cells including a first film and a second film whose permittivity is different from that of the first film which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines, and the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells.

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer, a first electrode, and a second electrode. The first switching layer includes a portion positioned between the first electrode and the conductive spacer, the second switching layer includes a portion positioned between the second electrode and the conductive spacer, and the conductive spacer is positioned between the portion of the first switching layer and the portion of the second switching layer.

In a non-volatile storage device, a first lower-layer metal wire, a lower plug, a variable resistance element, an upper plug, and a first upper-layer metal wire are formed in that order from below in a storage region, and a second lower-layer metal wire, a first via, a middle-layer metal wire, a second via, and a second upper-layer metal wire are formed in that order from below in a circuit region. The first and second lower-layer metal wires are formed in the same layer, and the first and second upper-layer metal wires are formed on the same layer. Relative to a substrate, the variable resistance element and the middle-layer metal wire have top faces at different heights, bottom faces at different heights, or both top faces and bottom faces at different heights.