An electronic device includes a structured metallization layer including a plurality of contact pads that are electrically isolated from one another, and a metal clip connected in a current shunt measurement arrangement with a semiconductor device, wherein the metal clip includes first, second and third landing pads, a first bridge span connected between the first and second landing pads, and second bridge span connected between the second and third landing pads, wherein the first, second third landing pads are respectively thermally conductively attached to first, second and third contact pads from the structured metallization layer, and wherein the second mounting pad is electrically floating.

The present invention relates to a circuit protection device including: a device comprising a heating element configured to comprise a body and a pair of electrodes formed on the body, and a pair of lead wires connected, respectively, to the pair of electrodes; and a case having an independent accommodating space formed therein to accommodate at least the heating element, wherein the case includes at least one heat insulating layer disposed in the vicinity of the accommodating space.

A chip resistor with a reduced thickness is provided. The chip resistor includes an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a second electrode electrically connected to the resistor. The first electrode and the second electrode are spaced apart from each other in a lateral direction that is perpendicular to the thickness direction of the substrate.

A chip resistor with a reduced thickness is provided. The chip resistor includes an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a second electrode electrically connected to the resistor. The first electrode and the second electrode are spaced apart from each other in a lateral direction that is perpendicular to the thickness direction of the substrate.

An electronic device includes a structured metallization layer including a plurality of contact pads that are electrically isolated from one another, and a metal clip connected in a current shunt measurement arrangement with a semiconductor device, wherein the metal clip includes first, second and third landing pads, a first bridge span connected between the first and second landing pads, and second bridge span connected between the second and third landing pads, wherein the first, second third landing pads are respectively thermally conductively attached to first, second and third contact pads from the structured metallization layer, and wherein the second mounting pad is electrically floating.

Provided is a varistor assembly capable of achieving good surge breakdown voltage while suppressing capacitance. The varistor assembly is obtained by connecting a plurality of varistor elements in parallel. Each varistor element includes: a sintered body obtained by sintering a laminate in which varistor layers and internal electrodes are alternately laminated; and a pair of external electrodes provided in a state where the internal electrodes are alternately connected on at least both end faces of this sintered body. Varistor element includes at least a plurality of first group varistor elements in which a value obtained by dividing a surface area of the sintered body by a volume of the sintered body is 1.9 mm.sup.−1 or more.

An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

The present invention is a load resistor that receives power transmitted from an apparatus and performs an energization test on the apparatus. The load resistor is characterized by comprising a rod-shaped resistive base body that is energized with the power and generates heat, a pipe-shaped protective member through which the rod-shaped resistive base body penetrates, and rod-shaped resistors having an insulation member that are packed in between the rod-shaped resistive base body and the protective member, the rod-shaped resistive base body having used therein a stretched nichrome wire that is wound in the shape of a coil.

A highly reliable surface-mounted resistor, which prevents a problem of disconnection between an electrode and a terminal of a chip resistor when heating during mounting, is disclosed. The surface-mounted resistor includes a chip resistor comprising a plate-shaped substrate, a resistance body formed on an upper surface of the substrate, and an electrode connected the resistance body and drawn from the upper surface of the substrate to a lower surface via an end surface, a plate-shaped lead terminal connected to the electrode of the chip resistor, the plate-shaped lead terminal being fixed to the electrode of the substrate on the lower surface side, and an exterior member covering an entire chip resistor and a part of the lead terminal.