A multilayer chip varistor includes an element body, first and second external electrodes, and first and second electrical conductor groups. The first electrical conductor group includes a first internal electrode connected to the first external electrode, and a first intermediate electrical conductor opposed to the first internal electrode. The second electrical conductor group includes a second internal electrode including a first electrically conductive material and connected to the second external electrode, and a second intermediate electrical conductor opposed to the second internal electrode. At least one of the first and second intermediate electrical conductors includes the second electrically conductive material. The element body includes a low electrical resistance region between the first and second internal electrodes. The second electrically conductive material is diffused in the low electrical resistance region.

A multilayer varistor according to the present disclosure includes: a sintered compact having, on a surface thereof, at least one planar portion and at least one corner portion; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the at least one planar portion and the at least one corner portion of the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes: a first high-resistivity layer covering the at least one planar portion; and a second high-resistivity layer covering the at least one corner portion. The first high-resistivity layer has a larger average thickness than the second high-resistivity layer.

A multilayer varistor according to the present disclosure includes; a sintered compact; an internal electrode provided inside the sintered compact; a high-resistivity layer arranged to cover the sintered compact at least partially; and an external electrode arranged to cover the high-resistivity layer partially and electrically connected to the internal electrode. The high-resistivity layer includes a thinner region having a smaller thickness than a surrounding region that surrounds the thinner region.

Provided are a resin composition for forming a varistor and a varistor capable of increasing freedom in the design of substrates, ICs, or electronics. The resin composition for forming a varistor includes (A) an epoxy resin, (B) a curing agent, (C) carbon nanotubes, and (D) a dispersant. The (C) carbon nanotubes may be single-walled carbon nanotubes, multi-walled carbon nanotubes, or a combination thereof. The (D) dispersant includes a polyalkyl oxide surfactant. The polyalkyl oxide surfactant has a polyalkyl ether skeleton in the molecule.

A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

In an embodiment, a component includes a first electrode and a second electrode arranged one above the other in a stacking direction, wherein the first electrode and the second electrode overlap in a first overlap region, wherein the first electrode has, in a first region containing the first overlap region, an extent in a first direction perpendicular to the stacking direction that is greater than an extent of the second electrode in the first direction in the first region, and wherein the first electrode has, in the first region containing the first overlap region, an extent in a second direction perpendicular to the stacking direction and to the first direction that is greater than an extent of the second electrode in the second direction in the first region, and a third electrode arranged in the same plane as the second electrode, wherein the first electrode is a floating electrode, wherein the first electrode and the third electrode overlap in a second overlap region, wherein the first electrode has, in a second region that contains the second overlap region, extents in the first direction and in the second direction that are greater than the extents of the third electrode in the first and the second direction in the second region, and wherein the first electrode has, in a connecting region that connects the first region and the second region, an extent in the first direction that is smaller than the extent of the first electrode in the first region and smaller than the extent of the first electrode in the second region.

A multilayer varistor according to the present disclosure includes a sintered compact, at least one pair of internal electrodes, and at least one pair of external electrodes. The sintered compact contains at least a Zn oxide and a Pr oxide. The at least one pair of internal electrodes are provided inside the sintered compact and contain, as a main component, at least one selected from the group consisting of Pd and Ag and, as a sub-component, an oxide of at least one element selected from the group consisting of Pr, Mn, Co, and Sb. The at least one pair of external electrodes are arranged to cover the sintered compact partially and electrically connected to the at least one pair of internal electrodes, respectively.

A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500° C. to 800° C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.

Provided is a varistor assembly capable of achieving good surge breakdown voltage while suppressing capacitance. The varistor assembly is obtained by connecting a plurality of varistor elements in parallel. Each varistor element includes: a sintered body obtained by sintering a laminate in which varistor layers and internal electrodes are alternately laminated; and a pair of external electrodes provided in a state where the internal electrodes are alternately connected on at least both end faces of this sintered body. Varistor element includes at least a plurality of first group varistor elements in which a value obtained by dividing a surface area of the sintered body by a volume of the sintered body is 1.9 mm.sup.−1 or more.

An electrical component having a layered structure including first and second electrodes each having first and second electrode portions located in a plane and at least partially embedded in a dielectric body, each of the first and second electrode portions separated by a gap and substantially isolated by the dielectric, the first electrode substantially parallel to and at least partially overlapping the second electrode, wherein the first and second electrodes are electrically isolated and separated by the dielectric body.