A varistor array can include a monolithic body including a plurality of dielectric layers. A first varistor can be formed in the monolithic body. The first varistor can include a first external terminal on a first end of the monolithic body, a first plurality of electrodes connected with the first external terminal, a second external terminal on a second end of the monolithic body, and a second plurality of electrodes connected with the second external terminal. The second plurality of electrodes can be interleaved with the first plurality of electrodes and can overlap the first plurality of electrodes at an overlapping area that is insensitive to a relative misalignment between the first plurality of electrodes and the second plurality of electrodes when the misalignment is less than a threshold. A second varistor can be formed in the monolithic body that is distinct from the first varistor.

A chip varistor includes an element body exhibiting varistor characteristics, internal electrodes containing a first electrically conductive material, and an intermediate conductor containing a second electrically conductive material. The intermediate conductor is separated from the internal electrodes in a direction in which the internal electrodes oppose each other, and is disposed between the internal electrodes. At least a part of the intermediate conductor overlaps the internal electrodes in the direction in which the internal electrodes oppose each other. The element body includes a low resistance region in which the second electrically conductive material is diffused. The low resistance region is located between the first and second internal electrodes in the direction in which the first and second internal electrodes oppose each other.

Disclosed are apparatus and a method for providing an integrated multiterminal multilayer ceramic device that has three or more capacitive elements. Two of such capacitive elements may be in series, with a third in parallel. The integrated device may be packaged as an overmolded three leaded component, or can be mounted as SMD (surface mount device). The integrated device may also be combined with a separate varistor in a stacked arrangement of leaded components.

A varistor includes an effective layer having first and second surfaces opposite to each other, a first ineffective layer stacked on the first surface of the effective layer, a second ineffective layer stacked on the second surface of the effective layer, and an external electrode. The effective layer includes a ceramic layer having a polycrystalline structure including crystal particles exhibiting voltage nonlinear characteristics, and internal electrodes stacked alternately on the ceramic layer. The thickness of the second ineffective layer is equal to or more than 1.1 times a thickness of the first ineffective layer and equal to or smaller than 6 times the thickness of the first ineffective layer. This varistor has a small size and excellent surge resistance.

A chip varistor includes an element body exhibiting varistor characteristics, internal electrodes containing a first electrically conductive material, and an intermediate conductor containing a second electrically conductive material. The intermediate conductor is separated from the internal electrodes in a direction in which the internal electrodes oppose each other, and is disposed between the internal electrodes. At least a part of the intermediate conductor overlaps the internal electrodes in the direction in which the internal electrodes oppose each other. The element body includes a low resistance region in which the second electrically conductive material is diffused. The low resistance region is located between the first and second internal electrodes in the direction in which the first and second internal electrodes oppose each other.

A chip varistor includes an element body exhibiting varistor characteristics, internal electrodes containing a first electrically conductive material, and an intermediate conductor containing a second electrically conductive material. The intermediate conductor is separated from the internal electrodes in a direction in which the internal electrodes oppose each other, and is disposed between the internal electrodes. At least a part of the intermediate conductor overlaps the internal electrodes in the direction in which the internal electrodes oppose each other. The element body includes a low resistance region in which the second electrically conductive material is diffused. The low resistance region is located between the first and second internal electrodes in the direction in which the first and second internal electrodes oppose each other.

A ceramic multi-layer component and a method for producing a ceramic multi-layer component are disclosed. In an embodiment a ceramic multi-layer component includes a stack with ceramic layers and electrode layers arranged between them, wherein the ceramic layers and the electrode layers are arranged above one another along a stacking direction, wherein at least one first electrode layer extends along a first main extension direction from a first end region to a second end region of the first electrode layer, and wherein the at least one first electrode layer has a current-carrying capacity that decreases along the first main extension direction.

A fuse device including a fuse component, a first electrode, disposed on a first side of the fuse component, a second electrode, disposed on a second side of the fuse component, and a phase change component, disposed in thermal contact with the fuse component. The fuse component may comprise a fuse temperature, wherein the phase change component exhibits a phase change temperature, the phase change temperature marking a phase transition of the phase change component, and wherein the phase change temperature is less than the fuse temperature.

A varistor is provided having a rectangular configuration defining first and second opposing end surfaces offset in a lengthwise direction. The varistor may include a first terminal adjacent the first opposing end surface and a second terminal adjacent the second opposing end surface. The varistor may include an active electrode layer including a first electrode electrically connected with the first terminal and a second electrode electrically connected with the second terminal. The first electrode may be spaced apart from the second electrode in the lengthwise direction to form an active electrode end gap. The varistor may include a floating electrode layer including a floating electrode. The floating electrode layer may be spaced apart from the active electrode layer in a height-wise direction to form a floating electrode gap. A ratio of the active electrode end gap to the floating electrode gap may be greater than about 2.

A chromaticity of zinc oxide is measured. The durability of a zinc oxide varistor is evaluated based on the chromaticity. This provides a varistor with a high durability stably.