A method of manufacturing a ceramic electronic component such that Voids of the ceramic element and voids at the interfaces between the ceramic element and the external electrodes are filled with a resin composition by applying, to the ceramic electronic component, a resin-containing solution that has the function of etching the surface of the ceramic element to ionize constituent elements of the ceramic element. The resin composition includes a resin, and cationic elements among the constituent elements of the ceramic elements, which are ionized and deposited from the ceramic element.

Provided are metal oxide varistors comprising a sintered ceramic, in which the ceramic comprises, by weight, about 91.0% to about 97.0% ZnO, at least 0.3% Mn, at least 0.4% Bi, at least 1.0% Sb, and 0.50% or less Co. The metal oxide varistors as disclosed herein may exhibit reduced power dissipation, improved thermal stability, and may be produced at a lower cost relative to conventional MOV devices.

Provided are metal oxide varistors comprising a sintered ceramic, in which the ceramic comprises, by weight, about 91.0% to about 97.0% ZnO, at least 0.3% Mn, at least 0.4% Bi, at least 1.0% Sb, and 0.50% or less Co. The metal oxide varistors as disclosed herein may exhibit reduced power dissipation, improved thermal stability, and may be produced at a lower cost relative to conventional MOV devices.

A multilayer varistor according to the present disclosure includes a sintered compact, at least one pair of internal electrodes, and at least one pair of external electrodes. The sintered compact contains at least a Zn oxide and a Pr oxide. The at least one pair of internal electrodes are provided inside the sintered compact and contain, as a main component, at least one selected from the group consisting of Pd and Ag and, as a sub-component, an oxide of at least one element selected from the group consisting of Pr, Mn, Co, and Sb. The at least one pair of external electrodes are arranged to cover the sintered compact partially and electrically connected to the at least one pair of internal electrodes, respectively.

Provided is a varistor assembly capable of achieving good surge breakdown voltage while suppressing capacitance. The varistor assembly is obtained by connecting a plurality of varistor elements in parallel. Each varistor element includes: a sintered body obtained by sintering a laminate in which varistor layers and internal electrodes are alternately laminated; and a pair of external electrodes provided in a state where the internal electrodes are alternately connected on at least both end faces of this sintered body. Varistor element includes at least a plurality of first group varistor elements in which a value obtained by dividing a surface area of the sintered body by a volume of the sintered body is 1.9 mm.sup.−1 or more.

The present invention relates to a polymer voltage-dependent resistor (PVDR) in various physical forms and methods for manufacturing the varistor. The body of the PVDR is composed of a polymer matrix having a filler composed of doped zinc oxide particles, other semi conductive particles or metal particles uniformly distributed therein. Conductive electrodes may be affixed to the polymer matrix and electrical leads attached to the electrodes.

A varistor includes an effective layer having first and second surfaces opposite to each other, a first ineffective layer stacked on the first surface of the effective layer, a second ineffective layer stacked on the second surface of the effective layer, and an external electrode. The effective layer includes a ceramic layer having a polycrystalline structure including crystal particles exhibiting voltage nonlinear characteristics, and internal electrodes stacked alternately on the ceramic layer. The thickness of the second ineffective layer is equal to or more than 1.1 times a thickness of the first ineffective layer and equal to or smaller than 6 times the thickness of the first ineffective layer. This varistor has a small size and excellent surge resistance.

A varistor includes an effective layer having first and second surfaces opposite to each other, a first ineffective layer stacked on the first surface of the effective layer, a second ineffective layer stacked on the second surface of the effective layer, and an external electrode. The effective layer includes a ceramic layer having a polycrystalline structure including crystal particles exhibiting voltage nonlinear characteristics, and internal electrodes stacked alternately on the ceramic layer. The thickness of the second ineffective layer is equal to or more than 1.1 times a thickness of the first ineffective layer and equal to or smaller than 6 times the thickness of the first ineffective layer. This varistor has a small size and excellent surge resistance.

A MOV device including a MOV chip, a first base metal electrode disposed on a first side of the MOV chip, and a second base metal electrode disposed on a second side of the MOV chip opposite the first side, each of the first base metal electrode and the second base metal electrode including a first base metal electrode layer disposed on a surface of the MOV chip and formed of one of silver, copper, and aluminum, the first base metal electrode layer having a thickness in a range of 2-200 micrometers, and a second base metal electrode layer disposed on a surface of the first base metal electrode layer and formed of one of silver, copper, and aluminum, the second base metal electrode layer having a thickness in a range of 2-200 micrometers.

A surge protective device (SPD) includes a first electrical terminal, a second electrical terminal, and an overvoltage protection circuit connected between the first and second electrical terminals. The overvoltage protection circuit includes a gas discharge tube and a current management circuit connected in series to the gas discharge tube. The current management circuit includes a varistor and a resistor that are connected in parallel between a first node of the current management circuit and a second node of the current management circuit.