Patent classifications
H01F10/3218
Magnetoelectric Computational Devices
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.
Recording read heads with a multi-layer AFM layer methods and apparatuses
Apparatuses and methods of recording read heads with a multi-layer anti-ferromagnetic (AFM) layer are provided. The AFM layer has gradient Manganese (Mn) compositions. A multi-layer AFM layer comprises a plurality of sub-layers having different Mn compositions. An upper sub-layer has a higher Mn composition than an lower sub-layer. Different types of gases may be used to deposit each sub-layer and the flow of each gas may be adjusted.
Magnetoelectric computational devices
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
VARIABLE-FREQUENCY MAGNETORESISTIVE EFFECT ELEMENT AND OSCILLATOR, DETECTOR, AND FILTER USING THE SAME
A variable-frequency magnetoresistive effect element includes a magnetoresistive effect element, a magnetic-field applying mechanism that applies a magnetic field to the magnetoresistive effect element, an electric-field applying mechanism that applies an electric field to the magnetoresistive effect element, and a control terminal connected to the electric-field applying mechanism and used for applying a voltage that varies in at least one of magnitude and polarity to the electric-field applying mechanism. The magnetoresistive effect element contains an antiferromagnetic material or ferrimagnetic material having a magnetoelectric effect. A spin torque oscillation frequency or spin torque resonance frequency of the magnetoresistive effect element is controlled by varying the voltage applied via the control terminal in at least one of magnitude and polarity.
PERMANENT MAGNET COMPRISING A STACK OF N PATTERNS
A permanent magnet including, at least once per group of ten consecutive ferromagnetic layers, a growth layer directly interposed between a top antiferromagnetic layer of a previous pattern and a bottom antiferromagnetic layer of a following pattern. This growth layer is entirely realized in a nonmagnetic material chosen from the group made up of the following metals: Ta, Cu, Ru, V, Mo, Hf, Mg, NiCr and NiFeCr, or it is realized by a stack of several sublayers of nonmagnetic material disposed immediately on one another, at least one of these sublayers being entirely realized in a material chosen from the group. The thickness of the growth layer is greater than 0.5 nm.
Magnetoelectric Computational Devices
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.
MAGNETIC MEMORY DEVICE HAVING COBALT-IRON-BERYLLIUM MAGNETIC LAYERS
Example embodiments relate to magnetic memory devices and methods for manufacturing the same. The magnetic memory device includes a magnetic tunnel junction layer including a first magnetic layer, a second magnetic layer, and a first tunnel barrier layer between the first and second magnetic layers. The second magnetic layer is disposed on the first tunnel barrier layer and is in direct contact with the first tunnel barrier layer. The second magnetic layer includes cobalt-iron-beryllium (CoFeBe). A beryllium content of CoFeBe in the second magnetic layer ranges from about 2 at % to about 15 at %.
MAGNETIC MEMORY CELLS AND SEMICONDUCTOR DEVICES COMPRISING THE MAGNETIC MEMORY CELLS
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication.
LAMINATED STRUCTURES FOR POWER EFFICIENT ON-CHIP MAGNETIC INDUCTORS
Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.
Laminated structures for power efficient on-chip magnetic inductors
Disclosed are magnetic structures, including on-chip inductors comprising laminated layers comprising, in order, a barrier and/or adhesion layer, a antiferromagnetic layer, a magnetic growth layer, a soft magnetic layer, an insulating non-magnetic spacer, a soft magnetic layer, a magnetic growth later, an antiferromagnetic layer. Also disclosed are methods of making such structures.