A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.

A semiconductor device having a first die and a second die is provided. The first die of the device includes a first surface and a through-substrate via (TSV) extending at least substantially through the first die, the TSV having a portion extending past the first surface. The first die further includes a first substantially helical conductor disposed around the TSV. The second die of the device includes a second surface, an opening in the second surface in which the portion of the TSV is disposed, and a second substantially helical conductor disposed around the opening.

Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.

A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.

A semiconductor device having 3D inductor includes a first transverse inductor, a longitudinal inductor and a second transverse inductor. The first transverse inductor is formed on a first substrate, the second transverse inductor and the longitudinal inductor are formed on a second substrate. The second substrate is bonded to the first substrate to connect the first transverse inductor and the longitudinal inductor such that the first transverse inductor, the longitudinal inductor and the second transverse inductor compose a 3D inductor.