Balun circuitry with a transceiver loop, a first antenna loop, and a second antenna loop is disclosed. The first antenna loop, the second antenna loop, and the transceiver loop are coaxially positioned such that the first antenna loop and the second antenna loop are coupled in opposite phase to the transceiver loop. In at least one exemplary embodiment, a semiconductor substrate has a layer that includes the first antenna loop, the second antenna loop, and the transceiver loop.

A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.

A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

A method is provided for fabricating thick silicon oxide structures, such as an embedded inductor. A Deep Reactive Ion Etch (DREI) etches the top silicon layer of a substrate to form high aspect ratio Si features, called trench texturing. The Si features are oxidized to form silicon oxide features. Adjacent Si features are separated by a trench width (S(0)), so that after oxidation, adjacent Si oxide features are formed separated by trench width (S(t)), where S(t)S(0) (e.g., S(t)=0). If the Si features have a width W.sub.Si(0)>1.2728 S(0), then the adjacent silicon oxide features form an amorphously merged silicon oxide feature with a planar top surface. The silicon oxide features have a height (H.sub.OX(t)) responsive to the trench width (S(0)), the Si feature width (W.sub.Si(t)), and the Si feature aspect ratio. After oxidation, inductor metal is deposited in trenches where W.sub.Si(0)<1.2728 S(0).

A T-coil IC includes a first inductor on an M.sub.x layer. The first inductor has n turns, where n is at least 1 turns. The T-coil IC further includes a second inductor on an M.sub.x1 layer. The second inductor has n turns. The first inductor and the second inductor are connected together at a node. The first inductor on the M.sub.x layer and the second inductor on the M.sub.x1 layer are mirror symmetric to each other. The T-coil IC further includes a center tap on an M.sub.x2y layer, where y0. The center tap is connected to the first inductor and the second inductor by a via stack at the node. In one configuration, n is 1+0.5z turns, where z0. An effective bridge capacitance of the T-coil IC may be approximately 25 fF.

A semiconductor element includes a first coil substantially located at a first plane; a second coil substantially located at the first plane; a connecting section that connects the first coil and the second coil; a third coil substantially located at a second plane different from the first plane; and a fourth coil substantially located at the second plane. The third coil and the first coil are connected through a through structure, and the fourth coil and the second coil are connected through a through structure. The third coil and the fourth are not directly connected.

A semiconductor element includes a first spiral coil, a second spiral coil, a connecting section, a first guide segment, and a second guide segment. The first spiral coil is formed with a first end and a second end, and includes a first inner turn and a first outer turn. The first inner turn is located in a range surrounded by the outer turn, and the first end and the second end are located at the first inner turn. The second spiral coil and the first spiral coil are located in substantially a same metal layer. The connecting section connects the first spiral coil and the second spiral coil. The first guide segment is connected to the first end. The second guide segment is connected to the second end. The first guide segment and the second guide segment are fabricated in a metal layer different from a metal layer of the first spiral coil.

A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

A module includes a wiring board, an insulating layer that is laminated on the bottom surface of the wiring board, a ring-shaped coil core that is embedded in the insulating layer, a coil electrode that is wound around the coil core, electronic components that are disposed in an inner region surrounded by the coil core in the insulating layer, and an electronic component that is mounted on or in the top surface of the wiring board. With this configuration, the areas of main surfaces of the wiring board and main surfaces of the insulating layer are not large, whereas if the electronic components were mounted on or in the top surface of the wiring board, the areas of the main surfaces of the wiring board and the main surfaces of the insulating layer would be large, and a reduction in the size of the module can be facilitated.