An inductor inlay, a component carrier, and methods for manufacturing the inductor inlay and the component carrier. The inductor inlay has a magnetic layer stack of interconnected magnetic layers and an electrically conductive structure embedded in the magnetic stack. The electrically conductive structure is configured as an inductor element with a coil-like shape. A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure and the inductor inlay with the magnetic layer stack with interconnected magnetic layers and the electrically conductive structure embedded in the magnetic layer stack. Methods for manufacturing the inductor inlay and component carrier are further described.

The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

A transformer respectively includes a first isolation barrier, a first inductive element, a second isolation barrier, and a second inductive element. The first isolation barrier and second isolation barrier each comprise multiple isolation layers. The transformer also includes magnetic material including a top magnetic portion disposed above the first isolation barrier. The transformer also includes a bottom magnetic portion disposed below the second inductive element; The transformer further includes an intermediary magnetic portion extending from the top magnetic portion to the bottom magnetic portion via a through-hole within the first isolation barrier, first inductive element, second isolation barrier, and second inductive element. The transformer yet further includes at least one lateral magnetic portion extending from the top magnetic portion to the bottom magnetic portion. The at least one lateral magnetic portion is disposed laterally from the first isolation barrier, first inductive element, second isolation barrier, and second inductive element.

An on-chip inductor includes a semiconductor substrate, a plurality of insulating layers stacked over the semiconductor substrate, and first, second and third spiral-shaped coil patterns. The first, second and third spiral-shaped coil patterns are inductively coupled to each other and sequentially disposed on respective layers among the plurality of insulating layers. Further, the first, second and third spiral-shaped coil patterns have respective first ends overlapping each other. The on-chip inductor further includes a first via connecting the respective first ends of the first and second spiral-shaped coil patterns to each other, and a second via connecting the respective first ends of the second and third spiral-shaped coil patterns to each other, where the first and second vias overlap each other.

The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.

An asymmetric spiral inductor fabricated in a semiconductor structure includes a spiral coil, a metal segment, and a connection structure. The spiral coil is substantially disposed in a first metal layer and includes a first terminal and a second terminal. The first terminal is disposed at an outermost turn of the spiral coil, and the second terminal is disposed at an innermost turn of the spiral coil. The metal segment is disposed in a second metal layer different from the first metal layer and has a third terminal and a fourth terminal. The connection structure connects the second terminal and the third terminal. The first terminal and the fourth terminal form the two terminals of the asymmetric spiral inductor. The spiral coil is a polygon with N sides (N>4). A portion of the metal segment has a shape substantially identical to a portion of the contour of the polygon.

An ESD protection element includes a semiconductor substrate, a wiring layer, and an inductor conductor. The semiconductor substrate includes a Zener diode. The inductor conductor is provided on the wiring layer and has a two-dimensional spiral shape. The inductor conductor includes a first inductor conductor and a second inductor conductor that are continuously provided from an outer peripheral end toward an inner peripheral end, and a connection conductor portion in a vicinity of a portion at which the first inductor conductor and the second inductor conductor are connected to each other. The second inductor conductor has a width smaller than a width of the first inductor conductor.

An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.

An asymmetric spiral inductor fabricated in a semiconductor structure includes a spiral coil, a metal segment, and a connection structure. The spiral coil is substantially disposed in a first metal layer and includes a first terminal and a second terminal. The first terminal is disposed at an outermost turn of the spiral coil, and the second terminal is disposed at an innermost turn of the spiral coil. The metal segment is disposed in a second metal layer different from the first metal layer and has a third terminal and a fourth terminal. The connection structure connects the second terminal and the third terminal. The first terminal and the fourth terminal form the two terminals of the asymmetric spiral inductor. The spiral coil is a polygon with N sides (N>4). A portion of the metal segment has a shape substantially identical to a portion of the contour of the polygon.