An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.

Fabricating composite monolithic structures to achieve optimal electrical, thermal, and mechanical properties through the elimination of air is discussed herein. A method of fabricating a composite structure includes coating an insulating layer with an uncured binding material and performing a first curing process on the uncured binding material to form a first stage cured binding material on the insulating layer without introduction of air pockets in a conventional manufacturing atmospheric environment. The method further includes disposing the insulating layer on an array of conductive structures. The first stage cured binding material is positioned between the insulating layer and the array of conductive structures. The method further includes performing a second curing process on the first stage cured binding material to form a cured binding material, and forming cured regions between adjacent conductive structures of the array of conductive structures.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

A circuit includes a first digital controlled oscillator and a second digital controlled oscillator coupled to the first digital controlled oscillator. A skew detector is connected to determine a skew between outputs of the first digital controlled oscillator and the second digital controlled oscillator, and a decoder is utilized to output a control signal, based on the skew, to modify a frequency of the first digital controlled oscillator using a switched capacitor array to reduce or eliminate the skew.

Power converters with integrated transformers and resonant inductors are described. An example power converter includes a primary-side converter stage, a number of secondary-side converter stages, and an integrated transformer and resonant inductor coupled between the primary-side and secondary-side converter stages. The integrated transformer includes a magnetic core having a first leg, an auxiliary leg, and a second leg. The integrated transformer also includes a first transformer having a first primary winding, a first secondary winding, and a first shield winding on the first leg, and a second transformer having a second primary winding, a second secondary winding, and a second shield winding on the second leg. The first shield winding is electrically coupled to provide an extension of the first primary winding for the first transformer, and an end of the first shield winding or the second shield winding is electrically coupled to a primary-side ground of the power converter.

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Methods and apparatus for isolation barrier with magnetics. In an example arrangement, an apparatus includes an isolation laminate including a dielectric core having a first surface and a second surface opposed to the first surface; at least one conductive layer configured as a first transformer coil overlying the first surface; a first dielectric layer surrounding the at least one conductive layer; a first magnetic layer overlying the at least one conductive layer; at least one additional conductive layer configured as a second transformer coil overlying the second surface; a second dielectric layer surrounding the at least one additional conductive layer; and a second magnetic layer overlying the at least one additional conductive layer. Methods for forming the isolation barriers and additional apparatus arrangements are also disclosed.

A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Exemplary embodiments of the present disclosure are related to inductor shielding. A device may include an inductor and a plurality of conductive strips extending across the inductor. At least a first conductive strip of the plurality of conductive strips is physically isolated from at least a second conductive strip of the plurality of conductive strips in a region of overlay of the first and second conductive strips.

An electronic device includes first leads along a first side, second leads along a second side, first and second dies, and a magnetic assembly with a multilevel lamination structure with first and second windings and a conductive guard trace. The lamination structure includes the first winding in a first level, and the second winding in a different level. The guard trace is between the first patterned conductive feature and the second side of the package structure. A first set of electrical connections couple the first die, the first winding, and one of the first conductive leads in a first circuit, and a second set of electrical connections couple the second die, the second winding, the guard trace and one of the second conductive leads in an isolated second circuit.