A circuit board with integrated fusing includes an insulating substrate having a circuit trace formed on a surface thereof, the circuit trace including a first circuit trace portion and a second circuit trace portion. A fusible link electrically connects the first circuit trace portion to the second circuit trace portion, the fusible link including a planar surface extending from the first circuit trace portion to the second circuit trace portion. A dielectric reflow encapsulates the fusible link on the planar surface from the first circuit trace portion to the second circuit trace portion.

A flexible printed circuit board (FPCB) including a pattern circuit layer. The pattern circuit layer has a pattern fuse embedded therein, and the pattern fuse includes a first conductive wire made of a metal and having a spiral structure, and a second conductive wire made of a metal and having a spiral structure. The first conductive wire and the second conductive wire have a double helix structure.

A high breaking capacity chip fuse including a bottom insulative layer, a first intermediate insulative layer, a second intermediate insulative layer, and a top insulative layer disposed in a stacked arrangement in the aforementioned order, a fusible element disposed between the first and second intermediate insulative layers and extending between electrically conductive first and second terminals at opposing longitudinal ends of the bottom insulative layer, the first intermediate insulative layer, the second intermediate insulative layer, and the top insulative layer, wherein the first and second intermediate insulative layers are formed of porous ceramic.

A circuit board with integrated fusing includes an insulating substrate having a circuit trace formed on a surface thereof, the circuit trace including a first circuit trace portion and a second circuit trace portion. A fusible link electrically connects the first circuit trace portion to the second circuit trace portion, the fusible link including a planar surface extending from the first circuit trace portion to the second circuit trace portion. A dielectric reflow encapsulates the fusible link on the planar surface from the first circuit trace portion to the second circuit trace portion.

A fuse resistor includes a substrate, an insulation layer, a fuse element, a protection layer, a first electrode, and a second electrode. The insulation layer covers a surface of the substrate. The fuse element is disposed on a portion of the insulation layer. The fuse element includes a first electrode portion, a melting portion, and a second electrode portion, in which the first electrode portion and the second electrode portion are respectively connected to two opposite ends of the melting portion. The protection layer covers the fuse element and the insulation layer, in which the protection layer has a cavity located on the melting portion. The first electrode is electrically connected to the first electrode portion. The second electrode is electrically connected to the second electrode portion.

A method of manufacturing a fuse includes stacking a base plate, an at least partially conductive fabric over the base plate and a cover layer over the fabric, each with an intervening bonding layer. At least one cavity is provided on both sides of the fabric, adjoining the fabric, between the respective edge regions. In addition, the fabric includes at least one first fiber which is electrically conductive and second fibers which are non-conductive and which have a lower melting temperature than the first fiber. The method further includes heating the stacked elements to a temperature below the melting temperature of the first fiber and above the melting temperature of the second fibers.

A surface-mountable thin-film fuse component is disclosed that may include a substrate having a top surface, a first end, and a second end that is spaced apart from the first end in a longitudinal direction. The thin-film component may include a fuse layer formed over the top surface of the substrate. The fuse layer may include a thin-film fuse track. An external terminal may be disposed along the first end of the substrate and electrically connected with the thin-film fuse track. The external terminal may include a compliant layer comprising a conductive polymeric composition.

A fuse resistor includes a substrate, an insulation layer, a fuse element, a protection layer, a first electrode, and a second electrode. The insulation layer covers a surface of the substrate. The fuse element is disposed on a portion of the insulation layer. The fuse element includes a first electrode portion, a melting portion, and a second electrode portion, in which the first electrode portion and the second electrode portion are respectively connected to two opposite ends of the melting portion. The protection layer covers the fuse element and the insulation layer, in which the protection layer has a concave located on the melting portion. The first electrode is electrically connected to the first electrode portion. The second electrode is electrically connected to the second electrode portion.

A surface mount device chip fuse including a dielectric substrate, electrically conductive first and second upper terminals disposed on a top surface of the dielectric substrate and defining a gap therebetween, a fusible element formed of solder disposed on the top surface of the dielectric substrate, within the gap, bridging the first and second upper terminals, and electrically conductive first and second lower terminals disposed on a bottom surface of the dielectric substrate and electrically connected to the first and second upper terminals, respectively, wherein a material of the dielectric substrate exhibits a de-wetting characteristic relative to the solder from which the fusible element is formed.

A fuse device for coupling terminals of battery cells are formed an ASEP manufacturing process. The fuse device is formed by stamping and forming a lead frame having first and second conductive plates extending into an opening thereof; overmolding a first insulative housing onto a first section of each of the plates without overmolding a second section of each of the plates, thereby coupling the plates together; forming a trace on the first insulative housing which is mechanically and electrically coupled to the plates; overmolding an insulative second housing over at least the trace thereby forming a subassembly; singulating the subassembly from the from the lead frame; mechanically and electrically coupling the second sections to third and fourth conductive plates.