Patent classifications
H01J19/24
Method of producing microrods for electron emitters, and associated microrods and electron emitters
Methods of producing microrods for electron emitters and associated microrods and electron emitters. In one example, a method of producing a microrod for an electron emitter comprises providing a bulk crystal ingot, removing a first plate from the bulk crystal ingot, reducing a thickness of the first plate to produce a second plate, and milling the second plate to produce one or more microrods. In another example, a microrod for an electron emitter comprises a microrod tip region that comprises a nanoneedle that in turn comprises a nanorod and a nanoprotrusion tip. The microrod and the nanoneedle are integrally formed from a bulk crystal ingot by sequentially: (i) removing the microrod from the bulk crystal ingot; (ii) coarse processing the microrod tip region to produce the nanorod; and (iii) fine processing the nanorod to produce the nanoprotrusion tip.
Method of producing microrods for electron emitters, and associated microrods and electron emitters
Methods of producing microrods for electron emitters and associated microrods and electron emitters. In one example, a method of producing a microrod for an electron emitter comprises providing a bulk crystal ingot, removing a first plate from the bulk crystal ingot, reducing a thickness of the first plate to produce a second plate, and milling the second plate to produce one or more microrods. In another example, a microrod for an electron emitter comprises a microrod tip region that comprises a nanoneedle that in turn comprises a nanorod and a nanoprotrusion tip. The microrod and the nanoneedle are integrally formed from a bulk crystal ingot by sequentially: (i) removing the microrod from the bulk crystal ingot; (ii) coarse processing the microrod tip region to produce the nanorod; and (iii) fine processing the nanorod to produce the nanoprotrusion tip.
Shaping nanomaterials by short electrical pulses
A dry-state non-contact method for patterning of nanostructured conducting materials is disclosed. Short self-generated electron-emission pulses in air at atmospheric pressure can enable an electron-emission-based (field enhancement) interaction between a sharp tungsten tip and elements of the nanostructured materials to cause largely non-oxidative sequential decomposition of the nanostructured elements. Embodiments can employ a substrate/tip gap of 10 to 20 nm, discharge voltages of 25-30 V, and patterning speeds as fast as 10 cm/s to provide precisely patterned nanostructures (<200 nm) that are largely free of foreign contaminants, thermal impact and sub-surface structural changes.
Shaping nanomaterials by short electrical pulses
A dry-state non-contact method for patterning of nanostructured conducting materials is disclosed. Short self-generated electron-emission pulses in air at atmospheric pressure can enable an electron-emission-based (field enhancement) interaction between a sharp tungsten tip and elements of the nanostructured materials to cause largely non-oxidative sequential decomposition of the nanostructured elements. Embodiments can employ a substrate/tip gap of 10 to 20 nm, discharge voltages of 25-30 V, and patterning speeds as fast as 10 cm/s to provide precisely patterned nanostructures (<200 nm) that are largely free of foreign contaminants, thermal impact and sub-surface structural changes.
Two-dimensional semiconductor with geometry structure and generating method thereof
A two-dimensional (2D) semiconductor with geometry structure and generating method thereof is disclosed herein and the method includes following steps: forming a nano-layer; disposing a 2D material on a substrate; forming a medium layer on the 2D material; transferring the medium layer and the 2D material to the nano-layer; removing the medium layer and leaving the 2D material on a surface of the nano-layer. In accordance with the generating method for 2D semiconductor with geometry structure, a nano microstructure is implemented to enhance and control the 2D materials for field emission and photon emission efficiency.
Two-dimensional semiconductor with geometry structure and generating method thereof
A two-dimensional (2D) semiconductor with geometry structure and generating method thereof is disclosed herein and the method includes following steps: forming a nano-layer; disposing a 2D material on a substrate; forming a medium layer on the 2D material; transferring the medium layer and the 2D material to the nano-layer; removing the medium layer and leaving the 2D material on a surface of the nano-layer. In accordance with the generating method for 2D semiconductor with geometry structure, a nano microstructure is implemented to enhance and control the 2D materials for field emission and photon emission efficiency.
Vertical metal-air transistor
A method of forming a vertical metal-air transistor device is provided. The method includes forming a precursor stack with a stack template on the precursor stack on a substrate. The method further includes forming a bottom spacer on the substrate around the precursor stack, and depositing a liner casing on the precursor stack. The method further includes depositing a conductive gate layer on the bottom spacer and liner casing. The method further includes reducing the size of the stack template to form a template post on the precursor stack, and forming a stack cap on the template post and precursor stack.
Vertical vacuum channel transistor
A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.
Vertical vacuum channel transistor
A vertical vacuum transistor with a sharp tip structure, and associated fabrication process, is provided that is compatible with current vertical CMOS fabrication processing. The resulting vertical vacuum channel transistor advantageously provides improved operational characteristics including a higher operating frequency, a higher power output, and a higher operating temperature while at the same time providing a higher density of vertical transistor devices during the manufacturing process.
Image intensifier with thin layer transmission layer support structures
A light intensifier includes a semiconductor structure to multiply electrons and block stray particles. A thin gain substrate layer includes an electron multiplier region that is doped to generate a plurality of electrons for each electron that impinges on an input surface of the gain substrate layer and blocking structures that are doped to direct the plurality of electrons towards emission areas of an emission surface of the gain substrate layer. Respective ribs of a first plurality of ribs on the input surface of the gain substrate layer are vertically aligned with respective blocking structures, and respective blocking structures are vertically aligned with respective ribs of a second plurality of ribs at the emission surface. This alignment directs electrons along a path through the gain substrate layer to reduce noise. The support ribs provide mechanical strength to the gain substrate layer, improving robustness of the light intensifier while minimizing noise.