A semiconductor analysis system includes a machining device that machines a semiconductor wafer to prepare a thin film sample for observation, a transmission electron microscope device that acquires a transmission electron microscope image of the thin film sample, and a host control device that controls the machining device and the transmission electron microscope device. The host control device evaluates the thin film sample based on the transmission electron microscope image, updates acquisition conditions of the transmission electron microscope image based on an evaluation result of the thin film sample, and outputs the updated acquisition conditions to the transmission electron microscope device

Embodiments of the present disclosure provide a grid structure. The grid structure includes a carrier and a support column; wherein the support column is located on the carrier, the support column has a top surface for supporting a sample; and the support column has a groove, the groove extends along a direction from the top surface to the carrier, and a groove wall of the groove is connected to the top surface.

A wafer support table includes a ceramic base having a wafer placement surface and including an RF electrode and a heater electrode embedded, the RF electrode being closer to the wafer placement surface; a hole extending from a surface of the ceramic base opposite the wafer placement surface toward the RF electrode; and an RF rod through having a top end joined to the RF electrode or joined to a conductive member connected to the RF electrode, wherein the RF rod is a hybrid rod including a first rod member that is made of Ni and constitutes a portion of the RF rod from the top end to a predetermined position and a second rod member that is joined to the first rod member and constitutes a portion of the RF rod from the predetermined position to the base end and is made of a non-magnetic material.

A lamella 10 including an analysis portion 11 and a cutout portion 12 separated from the analysis portion 11 is produced. When a plurality of the lamellae 10 are transported to a lamella grid 20, the plurality of lamellae 10 are supported by a support portion 22 protruding from a surface of a substrate 21, and are mounted adjacent to each other in a Z direction. At this time, the cutout portion 12 prevents the analysis portion 11 from damage.

A plasma processing apparatus includes an electrostatic chuck including an electrode, a first switch, a second switch, and a control unit. The control unit controls the first switch and the second switch to be in a closed state, causes a power supply to output a first voltage, and determines that the first switch and the second switch are in the closed state when the first voltage is detected by a detector. Further, after it is determined that the first switch and the second switch are in the closed state, the control unit controls the first switch and the second switch to be in an open state to start a processing of the substrate using the plasma in a state where the electrode is controlled to be in a floating state.

Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

Embodiments of the present disclosure relate to a system for pulsed direct-current (DC) biasing and clamping a substrate. In one embodiment, the system includes a plasma chamber having an electrostatic chuck (ESC) for supporting a substrate. An electrode is embedded in the ESC and is electrically coupled to a biasing and clamping network. The biasing and clamping network includes at least a shaped DC pulse voltage source and a clamping network. The clamping network includes a DC source and a diode, and a resistor. The shaped DC pulse voltage source and the clamping network are connected in parallel. The biasing and clamping network automatically maintains a substantially constant clamping voltage, which is a voltage drop across the electrode and the substrate when the substrate is biased with pulsed DC voltage, leading to improved clamping of the substrate.

Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include a heater embedded within the electrostatic chuck body. The substrate support assemblies may include a first bipolar electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The first bipolar electrode may include at least two separated mesh sections, with each mesh section characterized by a circular sector shape. The substrate support assemblies may include a second bipolar electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The second bipolar electrode may include a continuous mesh extending through the at least two separated mesh sections of the first bipolar electrode.

The present disclosure relates to methods and systems for chucking in substrate processing chambers. In one implementation, a method of chucking one or more substrates in a substrate processing chamber includes applying a chucking voltage to a pedestal. A substrate is disposed on a support surface of the pedestal. The method also includes ramping the chucking voltage from the applied voltage, detecting an impedance shift while ramping the chucking voltage, determining a corresponding chucking voltage at which the impedance shift occurs, and determining a refined chucking voltage based on the impedance shift and the corresponding chucking voltage.

A mounting table includes a wafer mounting surface mounting a wafer, a ring mounting surface disposed at a radially outer side of the wafer mounting surface and mounting a first ring having a first engaging portion and a second ring having a second engaging portion to be engaged with the first engaging portion, a lifter pin, and a driving mechanism. The second ring has a through-hole extends to reach a bottom surface of the first engaging portion, and the ring mounting surface has a hole at a position corresponding to the through-hole. A lifter pin has a first holding part that fits into the through-hole and a second holding part that extends from the first holding part and has a part protruding from the first holding part. The lifter pin is accommodated in the hole, and a driving mechanism vertically moves the lifter pin.