A method for producing a metal-ceramic substrate includes attaching a metal layer to a surface side of a ceramic layer, the metal layer being structured into a plurality of metallization regions respectively separated from one another by at least one trench-shaped intermediate space to form conductive paths and/or connective surfaces and/or contact surfaces. The method further includes filling the at least one trench-shaped intermediate space with an electrically insulating filler material, and covering first edges of the metallization regions facing and adjoining the surface side of the ceramic layer in the at least one trench-shaped intermediate space, as well as at least one second edge of the metallization regions facing away from the surface side of the ceramic layer in the at least one trench-shaped intermediate space, by the electrically insulating filler material.

A triggering condition is applied to a conductive polymer positioned in a drilled hole in a printed circuit board. The applied triggering condition causes the polymer to vertically expand within the drilled hole such that the expanded polymer creates an electrically conductive path between contact pads located in different layers of the printed circuit board.

Systems and methods for creating interlayer mechanical or electrical attachments or connections using filaments within a three-dimensional structure, structural component, or structural electronic, electromagnetic, or electromechanical component/device.

Vias may be established in printed circuit boards or similar structures and filled with a monolithic metal body to promote heat transfer. Metal nanoparticle paste compositions may provide a ready avenue for filling the vias and consolidating the metal nanoparticles under mild conditions to form each monolithic metal body. The monolithic metal body within each via can be placed in thermal contact with one or more heat sinks to promote heat transfer.

A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers such that the first portion has a first surface on first support plate side and a second surface, separating the first portion from the first plate, forming a conductor layer exposed on the first surface and including pads, laminating the first portion on a second support plate such that the second surface of the first portion faces second support plate side, forming on the first surface of the first portion a second laminated wiring portion including conductor and insulating layers such that the second portion has a third surface on second support plate side and a fourth surface, forming cavity in the second portion on the second plate such that the cavity exposes the pads, and separating the first and second portions from the second plate.

A process includes utilizing a pin array that includes multiple segmented pins for forming selectively plated through holes. The process includes forming a PCB laminate structure that includes multiple spinel-doped core layers and multiple through holes. Each spinel-doped core layer includes a heat-activated spinel material incorporated into a dielectric material. The process includes aligning individual segmented pins of a pin array with corresponding through holes of the PCB laminate structure, where each segmented pin includes heated segment(s) and insulating segment(s). The process includes inserting the segmented pins of the pin array into the corresponding through holes and generating heat within each heated pin segment that is sufficient to form metal nuclei sites in selected regions of the spinel-doped core layers adjacent to portions of the through holes that contain the heated pin segments. The metal nuclei sites function as seed layers to enable formation of selectively plated through holes.

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

A method of filling a hole formed in a component carrier with copper is disclosed. The method comprises i) forming a layer of an electrically conductive material covering at least part of a surface of a wall, wherein the wall delimits the hole, and subsequently ii) covering at least partially the layer and filling at least partially an unfilled volume of the hole with copper using a plating process including a bath. Hereby, the bath comprises a concentration of a copper ion, in particular Cu.sup.2+, in a range between 50 g/L and 75 g/L, in particular in a range between 60 g/L and 70 g/L.

A method produces a conductive paste comprising 15-20% by weight of PDMS and 80-85% by weight of metallic micro-nano particles, wherein the conductive paste is obtained by repeated addition of singular doses of PDMS to a heptane diluted PDMS low viscosity liquid containing the metallic micro-nano particles, wherein the heptane fraction is allowed to evaporate after addition of each of the singular doses of PDMS. A method forms a conductive path on a support layer, wherein the conductive path is encapsulated by an encapsulation layer comprising at least one via through which at least one portion of the conductive path is exposed, the method comprising filling the at least one via with the conductive paste.