Methods of forming variable-resistance devices include forming a variable-resistance layer between a first terminal and a second terminal from a material that varies in resistance based on an oxygen concentration. An electrolyte layer is formed over the variable-resistance layer from a material that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage. A conductive gate layer is formed over the electrolyte layer.

A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

Polysilicon films (P1,P2) are simultaneously formed on a wafer (W1) and a monitor wafer (W2) under the same growth condition in a wafer process. At least one of a film thickness and phosphorus concentration of the polysilicon film (P2) formed on the monitor wafer (W2) is measured to obtain a measured value. One of a plurality of mask patterns (A,B,C) is selected based on the measured value. The polysilicon film (P1) formed on the wafer (W1) is etched using the selected mask pattern to form the polysilicon resistor (5).

Embodiments of the present disclosure describe light emitting displays having a light emitter layer that includes an array of light emitters and a wafer having a driving circuit coupled with the light emitter layer, computing devices incorporating the light emitting displays, methods for formation of the light emitting displays, and associated configurations. A light emitting display may include a light emitter layer that includes an array of light emitters and a wafer coupled with the light emitter layer, where the wafer includes a driving circuit formed thereon to drive the light emitters. Other embodiments may be described and/or claimed.

Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.