A display apparatus may include a base substrate including a first portion and a second portion smaller than the first portion, a plurality of pixels disposed on the first portion, a protection substrate disposed below the base substrate, and a groove disposed in a portion of the protection substrate and overlapped with the second portion. The groove may include a first region extending in a first direction, and a second region and a third region, which are arranged along the first direction, wherein the first region is interposed between the second region and the third region. The first and second portions may be arranged in a second direction crossing the first direction, and a width of each of the second and third regions may be larger than a first width of the first region, when measured in the second direction.

The inventive concept provides an apparatus and method for treating a substrate with a gas. The apparatus includes a chamber having a process space in which the substrate is treated, a substrate support unit that supports the substrate in the process space, a gas supply unit that supplies a hydrophobic gas onto the substrate supported on the substrate support unit, and a controller that controls the substrate support unit and the gas supply unit. The substrate support unit includes a support plate on which the substrate is placed and a pin assembly that raises the substrate off the support plate or lowers the substrate onto the support plate, and the controller controls a degree of hydrophobization of a surface of the substrate by adjusting the pin assembly.

The method for doping a semiconductor includes the following steps in the following order: separation layer deposition step, in which a separation layer is deposited on the surface of a substrate, a mixture material source layer deposition step, in which a mixture material source layer including a mixture material is deposited on the separation layer, the mixture material of the mixture material source layer including a dopant substance, and annealing the substrate, the separation layer, and the mixture material source layer in an annealing step to arrange diffusion of dopant substance from the mixture material source layer to the substrate and to the separation layer.

Various embodiments of SST dies and solid state lighting (SSL) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.

A method of evaluating metal contamination by measuring the amount of metal contaminants to a silicon wafer in a rapid thermal processing apparatus includes steps of obtaining a Si single crystal grown by the Czochralski method at a pulling rate of 1.0 mm/min or lower, the crystal having oxygen concentration of 1.310.sup.18 atoms/cm.sup.3 or less, slicing silicon wafers from the Si single crystal except regions of 40 mm toward the central portion from the head of the single crystal and 40 mm toward the central portion from the tail, heat-treating the silicon wafer with a rapid thermal processing apparatus and transferring contaminants from members in a furnace of the rapid thermal processing apparatus to the silicon wafer, and measuring a lifetime of the silicon wafer to which contaminants are transferred.

In a semiconductor device, a semiconductor element is formed in a semiconductor, an interlayer insulating film having a contact hole and containing at least one of phosphorus and boron is disposed above the semiconductor, a metal electrode is disposed above the interlayer insulating film and is connected to the semiconductor element through the contact hole, and the interlayer insulating film is filled with hydrogen.

A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.

In an embodiment, a system includes a three-dimensional (3D) printer, a feedstock, and a laser. The three-dimensional printer includes a platen including an inert metal, and an enclosure including an inert atmosphere. The feedstock is configured to be deposited onto the platen. The feedstock includes a halogenated solution and a nanoparticle having negative electron affinity. The laser is configured to induce the nanoparticle to emit solvated electrons into the halogenated solution to form, by reduction, a ceramic and a diatomic halogen.

Variable-resistance devices and methods of forming the same include a variable-resistance layer, formed between a first terminal and a second terminal, that varies in resistance based on an oxygen concentration in the variable-resistance layer. An electrolyte layer that is stable at room temperature and that conducts oxygen ions in accordance with an applied voltage is positioned over the variable-resistance layer. A gate layer is configured to apply a voltage on the electrolyte layer and the variable-resistance layer and is positioned over the electrolyte layer.

An integrated circuit device includes: an integrated circuit module; a first field-effect transistor coupled between the integrated circuit module and a first reference voltage, and controlled by a first controlled signal; and a second field-effect transistor coupled between the integrated circuit module and the first reference voltage; wherein the second field-effect transistor is a complementary field-effect transistor of the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor are configured to generate a second reference voltage for the integrated circuit module according to the first control signal.