An optical element is provided. The optical element includes a substrate; a plurality of metal grids formed on the substrate; an oxide layer formed on the substrate between the plurality of metal grids; and a plurality of organic layers formed on the plurality of metal grids, wherein the width of the organic layer is greater than the width of the metal grid, and there is at least one gap between the organic layer and the oxide layer.

The present disclosure relates to: a MOSFET device which is applicable to a semiconductor device and, particularly, is manufactured using silicon carbide; and a manufacturing method therefor. The present disclosure provides a metal-oxide-semiconductor field effect transistor device which may comprise: a drain electrode; a substrate disposed on the drain electrode; an N-type drift layer disposed on the substrate; a plurality of P-type well layer regions disposed on the drift layer and spaced apart from each other to define a channel; an N+ region disposed on the well layer regions and adjacent to the channel; a P+ region disposed at the other side of the channel; a gate oxide layer disposed on the drift layer; a gate layer disposed on the gate oxide layer; and a source electrode disposed on the gate layer.

A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate. A first drift region is formed in the semiconductor substrate. A gate structure is formed on the semiconductor substrate A part of the gate structure covers a part of the first drift region. A first trench is formed in the first drift region, and a drain region is formed in the semiconductor substrate at the bottom of the first trench.

A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

An optoelectronic semiconductor chip including a semiconductor layer sequence containing a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region, a current spreading layer including a transparent conductive oxide adjoining the p-type semiconductor region, and a metallic p-connection layer at least regionally adjoining the current spreading layer, wherein the p-type semiconductor region includes a p-contact layer adjoining the current spreading layer, the p-contact layer contains GaP doped with C, a C dopant concentration in the p-contact layer is at least 5*10.sup.19 cm.sup.−3, and the p-contact layer is less than 100 nm thick.

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

A manufacturing method of a silicon carbide semiconductor device may include: forming a gate insulating film on a silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Methods for fabricating SiC MOSFETs using channeled ion implants are disclosed. By aligning the workpiece such that the ions pass through channels in the SiC hexagonal crystalline structure, it is possible to achieve deeper implants than are otherwise possible. Further, it was found that these channeled implants can be tailored to achieve box-like dopant concentrations. This allows channeled ion implants to be used to create the current spreading layer of the MOSFET, which is conventional fabricated using epitaxial growth. Further, these channeled implants can also be used to create the shields between adjacent transistors. Additionally, the use of channeled implants allows a reduction in the number of epitaxially growth processes that are used to create super junction MOSFETs.

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.