A measurement apparatus, a measurement compensation system, a measurement method and a measurement compensation method are provided. The measurement apparatus includes a jig wafer including: a wafer; a distance measuring sensor disposed on a front surface of the wafer and configured to measure a distance between the jig wafer and an upper electrode on the top of a reaction chamber after the jig wafer is placed on a wafer chuck of the reaction chamber; a horizontal sensor disposed on the front surface of the wafer and configured to measure the horizontal condition of the wafer chuck after the jig wafer is placed on the wafer chuck; and a data transmitting device connected with the distance measuring sensor and the horizontal sensor and configured to transmit the data measured by the distance measuring sensor and the data measured by the horizontal sensor.

A method for manufacturing a semiconductor device includes preparing a first substrate provided with a first pattern on a first surface, and a semiconductor chip having a second surface, and a third surface opposite to the second surface, and including a second pattern provided on the second surface, recognizing the first pattern from a position near the first surface among the first surface and an opposite surface thereof in the first substrate, recognizing the second pattern by transmitting through the semiconductor chip from a position near the third surface among the second surface and the third surface in the semiconductor chip, aligning the semiconductor chip and the first substrate based on a recognition result of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate so that the second surface faces the first surface.

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Methods and apparatus for increasing a bonded area between an ultrathin die and a substrate. In some embodiments, the method may include cleaning the die and the substrate, placing the die on an upper surface of the substrate, compacting the die to the substrate using a downward force of at least one compacting roller on the die and the upper surface of the substrate to increase a bonded area between the die and the upper surface of the substrate, and annealing the die and the substrate. The compacting roller has a soft surface layer that engages with the die and the upper surface of the substrate. The soft surface layer has a Shore hardness of greater than approximately 30 and less than approximately 80. In some embodiments, the substrate and/or the compacting roller may rotate during contact with each other.

Methods and apparatus for increasing a bonded area between an ultrathin die and a substrate. In some embodiments, the method may include cleaning the die and the substrate, placing the die on an upper surface of the substrate, compacting the die to the substrate using a downward force of at least one compacting roller on the die and the upper surface of the substrate to increase a bonded area between the die and the upper surface of the substrate, and annealing the die and the substrate. The compacting roller has a soft surface layer that engages with the die and the upper surface of the substrate. The soft surface layer has a Shore hardness of greater than approximately 30 and less than approximately 80. In some embodiments, the substrate and/or the compacting roller may rotate during contact with each other.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

Wafer alignment with restricted visual access has been disclosed. In an example, a method of processing a substrate for fabricating a solar cell involves supporting the substrate over a stage. The method involves forming a substantially opaque layer over the substrate. The substantially opaque layer at least partially covers edges of the substrate. The method involves performing fit-up of the substantially opaque layer to the substrate. The method involves illuminating the covered edges of the substrate with light transmitted through the stage, and capturing a first image of the covered edges of the substrate based on the light transmitted through the stage. The method further includes determining a first position of the substrate relative to the stage based on the first image of the covered edges. The substrate may be further processed based on the determined first position of the substrate under the substantially opaque layer.

A minimal contact end-effector is described that may be used for handling microelectronic and similar types of devices. In one example the end-effector has a vacuum pad to generate a lifting force and a standoff fastened to the vacuum pad. The standoff has a plurality of legs with chamfered edges to contact the edges of a microelectronic device to hold the device against the lifting force.