Disclosed are methods of fabricating semiconductor devices and methods of separating substrates. The semiconductor device fabricating method comprises providing a release layer between a carrier substrate and a first surface of a device substrate to attach the device substrate to the carrier substrate, irradiating the carrier substrate with an ultraviolet ray to separate the carrier substrate from the release layer and to expose one surface of the release layer, and performing a cleaning process on the one surface of the release layer to expose the first surface of the device substrate. The release layer includes an aromatic polymerization unit and a siloxane polymerization unit.

In an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.

A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A heater controller controls power supplied to a heater capable of adjusting the temperature of a placement surface such that the heater reaches a set temperature. A temperature monitor measures the power supplied in the non-ignited state where the plasma is not ignited and in the transient state where the power supplied to the heater decreases after the plasma is ignited, while the power is controlled such that the temperature of the heater becomes constant. A parameter calculator calculates a heat input amount and the thermal resistance by using the power supplied in the non-ignited state and in the transient state to perform a fitting on a calculation model for calculating the power supplied in the transient state. A set temperature calculator calculates the set temperature of the heater at which the wafer reaches the target temperature, using the heat input amount and thermal resistance.

An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; and a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool having a contact portion for contacting the die during a transfer from the die supply source to the substrate, the bond head including a spring portion engaged with the bond tool such that the spring portion is configured to compress during pressing of the die against the substrate using the contact portion of the bond tool.

A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

Methods and apparatus for protecting parts of a process chamber from thermal cycling effects of deposited materials. In some embodiments, a method of protecting the part of the process chamber includes wet etching the part with a weak alkali or acid, cleaning the part by bead blasting, coating at least a portion of a surface of the part with a stress relief layer. The stress relief layer forms a continuous layer that is approximately 50 microns to approximately 250 microns thick and is configured to preserve a structural integrity of the part from the thermal cycling of aluminum deposited on the part. The method may also include wet cleaning of the part with a heated deionized water rinse after formation of the stress relief layer.

A substrate support includes a supporting unit and a light irradiation mechanism. The supporting unit includes a plate member on which an inspection target is placed and a transparent member. The light irradiation mechanism is configured to irradiate light to increase a temperature of the inspection target. Each of the plate member and the transparent member is made of a low thermal expansion material having a linear expansion coefficient of 1.0×10.sup.−6/K or less.