A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

A volatile memory device can include a bit line structure having a vertical side wall. A lower spacer can be on a lower portion of the vertical side wall, where the lower spacer can be defined by a first thickness from the vertical side wall to an outer side wall of the lower spacer. An upper spacer can be on an upper portion of the vertical side wall above the lower portion, where the upper spacer can be defined by a second thickness that is less than the first thickness, the upper spacer exposing an uppermost portion of the outer side wall of the lower spacer.

Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.

Disclosed aspects include a semiconductor die including a substrate having a semiconductor surface including circuitry. A top metal layer is above the semiconductor surface including top metal lines that are electrically connected through a metal stack including metal interconnects that electrically connect to the circuitry. The top metal lines are configured in a primary orientation that collectively represents at least 50% of a total length of the top metal lines in a first direction. The top metal layer includes bond pads exposed from a passivation layer. The metal features are positioned lateral to and not directly electrically connected to the top metal layer and/or are positioned on the passivation layer. At least a majority of a total area of the metal features is not over metal interconnects. The metal features have a length direction oriented in a second direction that is at least essentially perpendicular relative to the primary orientation.

A system for designing a temperature sensor arrangement includes a processor and a non-transitory computer readable medium, including instructions, connected to the processor. The processor is configured to execute the instructions for designing a sensor array, the sensor array includes a first transistor of a first device, and a plurality of second transistors of a second device. The processor is configured to execute the instructions for designing a guard ring region between the sensor array and another circuit of an integrated circuit, the guard ring region includes a transistor structure. The processor is configured to execute the instructions for designing a thermally conductive element between the sensor array and the guard ring region, the thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors. The processor is configured to execute the instructions for generating the temperature sensor arrangement.

The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, forming a word line in the substrate, wherein the word line is intersected with the active region; forming a contact structure on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; sequentially forming a first conductive layer and a second conductive layer over the substrate, wherein the contact structure is covered by the first and second conductive layers; patterning the first and second conductive layers to form a conductive pillar and a landing pad, respectively, wherein the conductive pillar is overlapped with and electrically connected to the contact structure, the landing pad covers and electrically connects to the conductive pillar, and a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and forming a dielectric layer to laterally surround the conductive pillar and the landing pad.

An array substrate and a manufacturing method thereof are provided. A plurality of groups of bonding terminals are formed on a substrate, a first electrostatic protection wire is formed on a marginal region of the substrate, and a second electrostatic protection wire is formed to connect the bonding terminals and the first electrostatic protection wire.

An array substrate and a manufacturing method thereof are provided. A plurality of groups of bonding terminals are formed on a substrate, a first electrostatic protection wire is formed on a marginal region of the substrate, and a second electrostatic protection wire is formed to connect the bonding terminals and the first electrostatic protection wire.

The present invention provides a manufacturing method of an array substrate, including steps of: providing a flexible substrate layer, forming a buffer layer, forming an active layer, forming a gate insulating layer, forming a gate layer, forming an interlayer insulating layer, forming a source and drain layer, forming an organic planarization layer, forming an anode layer. An array substrate manufactured by the above manufacturing method, and the array substrate includes laminated a flexible substrate layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, an organic planarization layer, and an anode layer, which are disposed in a stack.

There may be provided a method of manufacturing a semiconductor chip. A layer stack in which first material layers and second material layers are alternately stacked is formed on a semiconductor substrate that includes a chip region and a scribe lane region, and crack propagation guides are formed in a first portion of the layer stack within the scribe lane region.