A design method of a metal mask, a manufacturing method of the metal mask and a computer-readable storage medium are provided. The design method of a metal mask includes: calculating amounts of deformations of the metal mask in two directions perpendicular to each other based on a stretching force of the metal mask in use and deformation properties of the metal mask in the two directions; and compensating the deformations of the metal mask in the two directions by compensation amounts for the deformations, which are identical and opposite to the amounts of the deformations of the metal mask in the two directions, respectively.

A method of identifying defects in an electronic assembly, comprising, by a processing unit, obtaining a grid of nodes representative of a location of electronic units of an electronic assembly, wherein each node is neighboured by at most eight oiler nodes, wherein a first plurality of nodes represents failed electronic units according to at least one test criterion, and a second plurality of nodes represents passing electronic units according to the least one first test criterion, based on the grid, determining at least one first and second straight lines, and attempting to connect the first and second straight lines into a new line, wherein if at least one node from the new line belongs to the second plurality of nodes, concluding that an electronic unit represented by the node on the grid is a failed electronic unit, thereby facilitating identification of a failed electronic unit on the substrate.

A device manufacturing method, the method comprising: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.

A method is provided for fabricating and inspecting a photovoltaic assembly including a base, at least one photovoltaic module, and at least one adhesion layer based on a crosslinkable polymer material. The method includes depositing the at least one adhesion layer on the base; an assembly step; a partial crosslinking step; an electrical connection step; inspecting for mechanical and electrical functioning; in the event of correct functioning being detected, a crosslinking finalization step; in the event of incorrect functioning being detected removing at least one defective photovoltaic module.

Metrology targets and methods are provided, which comprise at least two overlapping structures configured to be measurable in a mutually exclusive manner at least at two different corresponding optical conditions. The targets may be single cell targets which are measured at different optical conditions which enable independent measurements of the different layers of the target. Accordingly, the targets may be designed to be very small, and be located in-die for providing accurate metrology measured of complex devices.

Systems, method and related apparatuses for adjusting support elements of a support apparatus to approximate a surface profile of a wafer. The support apparatus may include a group of mutually lateral adjacent support elements, each mutually lateral adjacent support element is configured to independently move at least vertically and comprising an upper surface. The support apparatus may further include a thermal energy transfer device operably coupled to each of the mutually lateral support elements, and an actuator system operably coupled to each of the support elements to selectively move one or more of the mutually lateral support elements vertically.

Disclosed is a method for producing a wafer map. More specifically, the present invention relates to: a method for producing a wafer map used for manufacturing chips in the semiconductor field, wherein a geographic information system (GIS) technique is used to produce the wafer map; and a method and system for providing wafer test results using same. According to an embodiment of the present invention, a semiconductor wafer is formed as a map by using the GIS technique, a coordinate system used in the GIS is utilized to create a map of the same size as an actual semiconductor wafer, and each of various constituent elements constituting the wafer can be stratified to reflect the actual size of the element to create a wafer map in which each of the elements is geocoded.

Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

The present disclosure is a substrate processing apparatus including: a chamber configured to accommodate a substrate; a heat source configured to heat-treat the substrate; a heat ray sensor provided outside the chamber and configured to receive infrared rays radiated from the substrate; and an infrared ray transmission window provided in the chamber and configured to transmit an infrared ray having a wavelength greater than or equal to 8 μm to the heat ray sensor.

Semiconductor structures and methods of testing the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a semiconductor device over the substrate, wherein the semiconductor device includes an interconnect structure, and the interconnect structure includes a plurality of metallization layers disposed in a dielectric layer; and a delamination sensor. The delamination sensor includes a connecting structure and a plurality of contact vias in at least one of the plurality of metallization layers. The connecting structure bonds the semiconductor device to the substrate and does not functionally couple the semiconductor device to the substrate. The plurality of contact vias fall within a first region of a vertical projection area of the connecting structure but do not overlap a second region of the vertical projection area.