The present description concerns an electronic die manufacturing method comprising: a) the deposition of an electrically-insulating resin layer on the side of a first surface of a semiconductor substrate, inside and on top of which have been previously formed a plurality of integrated circuits, the semiconductor substrate supporting on a second surface, opposite to the first surface, contacting pads; and b) the forming, on the side of the second surface of the semiconductor substrate, of first trenches, electrically separating the integrated circuits from one another, the first trenches vertically extending in the semiconductor substrate and emerging into or on top of the resin layer.

A white light illumination source can illuminate a region of a substrate to be plasma etched with an incident light beam. A camera takes successive images of the region being illuminated during a plasma etch process. Image processing techniques can be applied to the images so as to identify a location of at least one feature on the substrate and to measure a reflectivity signal at the location. The plasma etch process can be modified in response to the measured reflectivity signal at the location.

An optical inspection is performed to detect potential defects within integrated circuit devices and a first electron-based inspection of less than all of the potential defects is performed to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified and the integrated circuit devices manufactured using the manufacturing parameter settings inside the process window have less than a threshold number of the primary actual defects. To identify additional actual defects a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices that were manufactured using the manufacturing parameter settings inside the process window but were uninspected in the first electron-based inspection.

There is provided a system and method of measuring a lateral recess in a semiconductor specimen, comprising: obtaining a first image acquired by collecting SEs emitted from the surface of the specimen, and a second image acquired by collecting BSEs scattered from an interior region of the specimen between the surface and a target second layer, the specimen scanned using an electron beam with a landing energy selected to penetrate to a depth corresponding to the target second layer; generating a first GL waveform based on the first image, and a second GL waveform based on the second image; estimating a first width of the first layers based on the first GL waveform, and a second width with respect to at least the target second layer based on the second GL; and measuring a lateral recess based on the first width and the second width.

A method includes depositing an inter-metal dielectric (IMD) layer over a conductive line. A via opening is formed in the IMD layer and directly over the conductive line. A width of the conductive line is greater than a width of the via opening. An overlay measurement is performed. The overlay measurement includes obtaining a backscattered electron image of the via opening and the conductive line and determining an overlay between the via opening and the conductive line according to the backscattered electron image.

The first layer mark and the second layer mark are adapted to be projected onto each other during the lithographic process. The first layer components and the second layer components are adapted to be arranged in a plurality of different overlay configurations, each overlay configuration comprising a number of the plurality of the first layer components and a number of the plurality of the second layer components, and each overlay configuration having a different overlay distance at which each first layer component is arranged in a first direction of an associated second layer component of the second layer components. The method comprises determining an overlay step which represents a difference between the different overlay distances of the plurality of overlay configurations, determining a largest overlay distance, determining the number of first layer components and/or the number of associated second layer components in each overlay configuration.

A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

A measurement device and method for a semiconductor structure are provided. The measurement device for the semiconductor structure includes a bearing platform, a clamping mechanism, and an image acquisition system. The clamping mechanism is installed on the bearing platform and includes a clamp disposed along a vertical direction. The clamp is configured to clamp the semiconductor structure such that the semiconductor structure is clamped with a to-be-measured surface facing a side. The image acquisition system is disposed by a side of the clamping mechanism, and is configured to acquire a three-dimensional morphology of the semiconductor structure from the side.

A semiconductor substrate includes a buried semiconductor layer and semiconductor wells. A device for detecting a possible thinning of the semiconductor substrate via the rear face thereof is formed on and in the semiconductor wells. The device is a non-inverting buffer including an input terminal and an output terminal, the device being powered between a supply terminal and a reference terminal where the buried semiconductor layer provides the supply terminal. A control circuit delivers an input signal in a first state to the input terminal and outputs a control signal indicating a detection of a thinning of the substrate if a signal generated at the output terminal in response to the input signal is in a second state different from the first state.

A semiconductor structure with backside through silicon vias (TSVs) is provided in the present invention, including a semiconductor substrate with a front side and a back side, multiple dummy pads set on the front side, multiple backside TSVs extending from the back side to the front side, wherein a number of the dummy pads are connected with the backside TSVs while other dummy pads are not connected with the backside TSVs, and a metal coating covering the back side and the surface of backside TSVs and connected with those dummy pads that connecting with the backside TSVs.