Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

When a chip, or manufactured integrate circuit, is found to have a portion that is defective, “floorsweeping” may be used to salvage the working portion of the chip. Floorsweeping involves downgrading, or turning off, the portion of the chip with the defect and then operating the remaining portion of the chip as a lower quality chip than the larger chip that was originally intended. In use, applications will then only use the active portion of the chip. However, the resulting lower quality chip will still have the same static leakage of the larger, non-defective chip. This leakage results from a voltage still being applied to the entire area of the larger chip, even though a portion of that area has been downgraded. The present disclosure provides a method for processing defective chips to form a smaller chip that avoids the excess static leakage associated with floorsweeping by physically removing the defective portion of the chip.

An image-forming element includes a plurality of pixels, and projects and displays light emitted from the pixels. The image-forming element includes a light emitting element which includes a light source emitting the light and a mounting substrate on which a plurality of light emitting elements are provided on a mounting surface. A plurality of light sources which are segmented and included in at least one pixel are provided, and each of the light sources includes power supply electrodes provided on the same surface or a surface facing the mounting substrate. The mounting substrate includes a drive circuit which drives the light source and electrodes which are provided on the mounting surface and are electrically connected to the power supply electrodes of the light source. In each pixel, an area occupation ratio of the light source with respect to a region area of the pixel is 15% or more and 85% or less. The drive circuit includes a switch circuit which selectively short-circuits the electrodes electrically connected to the power supply electrodes of the light source with other electrodes or wirings in the drive circuit, or at least one non-volatile memory transistor for adjusting a light emission intensity of the light emitting element.

What is disclosed are structures and methods for testing and repairing emissive display systems. Systems are tested with use of temporary electrodes which allow operation of the system during testing and are removed afterward. Systems are repaired after identification of defective devices with use of redundant switching from defective devices to functional devices provided on repair contact pads. Time varying signals coupled to a capacitor are used as well.

Implementations of a method for healing a crack in a semiconductor substrate may include identifying a crack in a semiconductor substrate and heating an area of the semiconductor substrate including the crack until the crack is healed.

The present disclosure relates to a method of manufacturing shingled solar module and the shingled solar module. The method includes steps of: arranging solar cells and conductive sheets on a top surface of a bottom package feature along a second direction in a shingled manner into a plurality of solar cell strings, wherein the conductive sheets are disposed at trailing ends of the solar cell strings, and the solar cell strings are arranged along a first direction perpendicular to the second direction to form a cell array; arranging a first busbar and a second busbar on a top or a bottom or the cell array, where the first busbar is in contact with main grid lines of the solar cells at initial ends of the respective solar cell strings, and the second busbar is in electrical contact with the conductive sheets of the respective solar cell strings; and laminating a combined feature comprised of the top package feature, the cell array, and the bottom package feature. In the method according to the present disclosure, the arranging step and the shingling step are combined as one step, in which the cells are shingled and arranged directly on the bottom package feature . In this way, the method is advantageous for operation and can be implemented efficiently at low costs.

A method includes forming a set of through-vias in a substrate, the set of through-vias partially penetrating a thickness of the substrate. First connectors are formed over the set of through-vias on a first side of the substrate. The substrate is singulated to form dies. The first side of the dies are attached to a carrier. The dies are thinned from the second side to expose the set of through-vias. Second connectors are formed over the set of through-vias on the second side of the dies. A device die is bonded to the second connectors. The dies and device dies are singulated into multiple packages.

A wafer manufacturing method includes a wafer preparing step of preparing a wafer partitioned into a plurality of separate areas by a plurality of crossing streets, the wafer including a plurality of semiconductor devices respectively formed in the plural separate areas, a removing step of determining whether each semiconductor device formed in the wafer is an acceptable product or a defective product and removing a defective device area including the semiconductor device determined as the defective product, from the wafer, and a fitting step of fitting a device chip adapted to be fitted into a space formed by the removal of the defective device area from the wafer into the space of the wafer, the device chip including an acceptable semiconductor device having the same function as that of the semiconductor device determined as the defective product.

Disclosed herein is an apparatus that includes a first semiconductor chip, first and second TSVs penetrating the first semiconductor chip, a first path including the first TSV, a second path including the second TSV, a first charge circuit configured to charge the first path, a second charge circuit configured to charge the second path, a first discharge circuit configured to discharge the first path, a second discharge circuit configured to discharge the second path, and a comparator circuit configured to compare a potential of the first path with a potential of the second path.