Patent classifications
H01L22/24
Pressure-activated electrical interconnection with additive repair
A method of making a repaired electrical connection structure comprises providing a substrate having first and second contact pads electrically connected in parallel, providing first and second functionally identical components, disposing a first adhesive layer on the substrate, transferring the first component onto the first adhesive layer, electrically connecting the first component to the first contact pad, testing the first component to determine if the first component is a faulty component and, if the first component is a faulty component, disposing a second adhesive layer on the substrate and transferring the second component onto the second adhesive layer, and electrically connecting the second component to the second contact pad. The first and second adhesive layers can be unpatterned or patterned and the first and second components can be electrically connected to the first and second contact pads, respectively, with connection posts or photolithographically defined electrodes.
Pressure-activated electrical interconnection with additive repair
A method of making a repaired electrical connection structure comprises providing a substrate having first and second contact pads electrically connected in parallel, providing first and second functionally identical components, disposing a first adhesive layer on the substrate, transferring the first component onto the first adhesive layer, electrically connecting the first component to the first contact pad, testing the first component to determine if the first component is a faulty component and, if the first component is a faulty component, disposing a second adhesive layer on the substrate and transferring the second component onto the second adhesive layer, and electrically connecting the second component to the second contact pad. The first and second adhesive layers can be unpatterned or patterned and the first and second components can be electrically connected to the first and second contact pads, respectively, with connection posts or photolithographically defined electrodes.
APPARATUS AND METHODS FOR THREE DIMENSIONAL RETICLE DEFECT SMART REPAIR
One or more embodiments of the present disclosure describe an artificial intelligence assisted substrate defect repair apparatus and method. The AI assisted defect repair apparatus employs an object detection algorithm. Based on the plurality of images taken by detectors located at different respective positions, the detectors capture various views of an object including a defect. The composition information as well as the morphology information (e.g., shape, size, location, height, depth, width, length, or the like) of the defect and the object are obtained based on the plurality of images. The object detection algorithm analyzes the images and determines the type of defect and the recommends a material (e.g., etching gas) and the associated information (e.g., supply time of the etching gas, flow rate of the etching gas, etc.) for fixing the defect.
Repair techniques for micro-LED devices and arrays
What disclosed are structures and methods for repairing emissive display systems. Various repairing techniques embodiments in accordance with the structures and methods are provided to conquer and mitigate the defected pixels and to increase the yield and reduce the cost of emissive displays systems.
Wafer table with dynamic support pins
A method for fabricating a wafer includes providing a wafer table, wherein the wafer table includes support pins that are movable with respect to each other; identifying features of a layer to be formed on a wafer, wherein the features have a tolerance for overlay errors below a threshold; moving one or more support pins based on the features; after the moving of the one or more support pins, mounting the wafer on the wafer table; and after the mounting of the wafer on the wafer table, forming the layer on the wafer.
In-situ metrology and process control
Methods and apparatus for the in-situ measurement of metrology parameters are disclosed herein. Some embodiments of the disclosure further provide for the real-time adjustment of process parameters based on the measure metrology parameters. Some embodiments of the disclosure provide for a multi-stage processing chamber top plate with one or more sensors between process stations.
Testing of LED devices during pick and place operations
A pick and place LED testing apparatus, comprising: a test station operative in use to power a group of LEDs; a bondhead operative in use to pick said group of LEDs from a source wafer and place said group of LEDs on said test station for testing; and an optical sensor operative in use to measure an optical characteristic of said group of LEDs when tested, wherein at least a portion of said bondhead is translucent to provide an optical path from said group of LEDs to said optical sensor.
Electronic device and method for manufacturing electronic device
A method for manufacturing an electronic device includes: providing a substrate; forming a plurality of connecting pads and a plurality of conductive portions partially overlapped by the plurality of connecting pads on the substrate; forming a plurality of conductive lines on the substrate, wherein one of the plurality of conductive lines is partially overlapped with one of the plurality of conductive portions, and an insulating layer is disposed between one of the plurality of connecting pads and the one of the plurality of conductive portions; and bonding a plurality of light emitting units to the plurality of connecting pads.
METHOD OF MONITORING A SEMICONDUCTOR DEVICE FABRICATION PROCESS AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME
Disclosed are a method of monitoring a semiconductor device fabrication process and a method of fabricating a semiconductor device using the same. The monitoring method may include determining a normalization range of a target byproduct, which is a measurement target of byproducts produced in a chamber by an etching process, the byproducts including the target byproduct and a non-target byproduct, the target byproduct including first and second target byproducts, which are respectively produced by and before the etching process on a to-be-processed layer, obtaining a first index from a ratio of the target byproduct to the non-target byproduct, obtaining a second index by subtracting an emission intensity of the second target byproduct from the first index, obtaining a third index by integrating the second index on a time interval, and estimating a result of the etching process and presence or absence of a failure, based on the third index.
DEFECT REMOVAL DEVICE, DEFECT REMOVAL METHOD, PATTERN FORMING METHOD, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
Provided are a defect removal device and a defect removal method capable of removing defects of a semiconductor substrate with high accuracy, and a pattern forming method and a method of manufacturing an electronic device using the semiconductor substrate from which defects on a surface are removed. The defect removal device includes: a first light source unit that emits incidence light for detecting a defect on a semiconductor substrate; a surface defect measurement unit including a detection unit that detects the defect on the semiconductor substrate based on radiated light radiated by reflection or scattering of the incidence light from the defect of the semiconductor substrate; a removal unit that irradiates the semiconductor substrate with laser light to remove the defect based on position information of the defect on the semiconductor substrate; and an alignment unit that adjusts optical axes of the incidence light and the laser light, in which the optical axes of the incidence light and the laser light are adjusted by the alignment unit such that the incidence light and the laser light are emitted to the semiconductor substrate.