Patent classifications
H01L22/26
POSITION DETECTION AND DETERMINATION DEVICE AND POSITION CALIBRATION DEVICE AND METHOD
A position detection and determination device and a position calibration device and method are provided. The position detection and determination device includes a standard positioning pin position limiting component configured to limit standard position information of a positioning pin of a load port of a silicon wafer pod; a positioning pin position detecting component configured to detect real-time position information of the positioning pin of the load port of the silicon wafer pod; and a determining module configured to obtain the standard position information and the real-time position information, and determine whether the position of the positioning pin of the load port of the silicon wafer pod is accurate or not according to the standard position information and the real-time position information.
VIRTUAL METROLOGY FOR FEATURE PROFILE PREDICTION IN THE PRODUCTION OF MEMORY DEVICES
To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.
Optical diagnostics of semiconductor process using hyperspectral imaging
Disclosed are embodiments of an improved apparatus and system, and associated methods for optically diagnosing a semiconductor manufacturing process. A hyperspectral imaging system is used to acquire spectrally-resolved images of emissions from the plasma, in a plasma processing system. Acquired hyperspectral images may be used to determine the chemical composition of the plasma and the plasma process endpoint. Alternatively, a hyperspectral imaging system is used to acquire spectrally-resolved images of a substrate before, during, or after processing, to determine properties of the substrate or layers and features formed on the substrate, including whether a process endpoint has been reached; or before or after processing, for inspecting the substrate condition.
Processing method of workpiece with laser power adjustment based on thickness measurement and processing apparatus thereof
A processing method of a workpiece used when the workpiece is processed is provided. The processing method of a workpiece includes a disposing step of disposing the workpiece in a gas containing a substance that generates an active species that reacts with the workpiece, a measurement step of measuring the distribution of the thickness of the workpiece disposed in the gas, and a laser beam irradiation step of irradiating the workpiece in the gas with a laser beam of which the power is adjusted based on the distribution of the thickness measured in the measurement step. In the laser beam irradiation step, the removal amount by which a region irradiated with the laser beam in the workpiece is removed by the active species is controlled by irradiating the workpiece with the laser beam of which the power is adjusted.
PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
A plasma processing apparatus and method with an improved processing yield, the plasma processing apparatus including detector configured to detect an intensity of a first light of a plurality of wavelengths in a first wavelength range and an intensity of a second light of a plurality of wavelengths in a second wavelength range, the first light being obtained by receiving a light which is emitted into the processing chamber from a light source disposed outside the processing chamber and which is reflected by an upper surface of the wafer, and the second light being a light transmitted from the light source without passing through the processing chamber; and a determination unit configured to determine a remaining film thickness of the film layer by comparing the intensity of the first light corrected using a change rate of the intensity of the second light.
APPARATUS AND METHODS FOR DETERMINING FLUID DYNAMICS OF LIQUID FILM ON WAFER SURFACE
An apparatus for inspecting a semiconductor substrate includes a rotatable base configured to support a substrate, and a nozzle arm includes a nozzle and a light monitoring device. The light monitoring device includes a laser transmitter and an array of light sensors arranged in the nozzle arm and facing the substrate. The light monitoring device is configured to transmit a laser pulse towards the substrate, wherein the laser pulse impinges on the substrate, receive a reflected laser pulse from the substrate, calculate whether one or more light sensors received the laser pulse, and calculate a distance between the light monitoring device and the substrate using the turnaround time for determining a process quality on the substrate.
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.
CRITICAL DIMENSION ERROR ANALYSIS METHOD
The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD″) values, according to relative error between CD″ and CD, dividing the rebuilt critical dimension (CD″) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results. The present invention uses an outer limit to remove extreme outliers, so as to analyze a critical dimension error during a lithography process quickly and accurately.
Substrate processing apparatus, substrate processing method, and computer-readable recording medium
An end of polishing of a wafer is determined for each of wafers at a high accuracy. A wafer processing method includes: a first process of acquiring an initial state of a processing target surface of a wafer; a second process of forming a coating film on the wafer after the first process; a third process of polishing the processing target surface of the wafer by a polishing member based on initial polishing conditions in a state where the polishing member is in contact with the processing target surface of the wafer; a fourth process of acquiring a processed state of the processing target surface of the wafer after the third process; and a fifth process of determining an end of polishing, an insufficiency in polishing, or an excess in polishing based on the initial state and the processed state.
SEMICONDUCTOR DEVICE PACKAGING WARPAGE CONTROL
A method of manufacturing a packaged semiconductor device is provided. The method includes placing a plurality of semiconductor die on a carrier substrate. The plurality of semiconductor die and an exposed portion of the carrier substrate are encapsulated with an encapsulant. A cooling fixture includes a plurality of nozzles and is placed over the encapsulant. The encapsulant is cooled by way of air exiting the plurality of nozzles. A property of air exiting a first nozzle of the plurality of nozzles is different from that of a second nozzle of the plurality of nozzles.