Provided are a semiconductor wafer and a test method. The semiconductor wafer includes a substrate including multiple die regions and scribe line regions positioned between adjacent die regions; circuit test devices, positioned in the scribe line regions and provided with multiple test ports; anti-crack conductive structures, positioned in the scribe line regions and around the die regions, and positioned between the circuit test devices and the die regions; and at least one first wire for each circuit test device, one end of the first wire being connected to the corresponding test port, and the other end of the first wire being connected to the adjacent anti-crack conductive structure. The embodiments solve the problem of lack of wiring space for wires in the scribe line regions by utilizing the anti-crack conductive structures to provide test signals to the circuit test devices.

Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

A method for electrically characterizing a layer disposed on a substrate and electrically insulated from the substrate is disclosed. The method can include forming a test pattern, contacting the test pattern with electrical contact elements at contact regions, and measuring an electrical parameter of the layer by passing a first set of test currents between contact regions. The test pattern can be formed by pushing a pattern forming head against a top surface of the layer, introducing a first fluid into the cavity, and converting the sacrificial portion of the layer into an insulator using the first fluid and forming the test pattern under the test-pattern-shaped inner seal.

A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

A semiconductor device includes: a substrate; a test transistor over the substrate; and multi-level metal interconnections formed over the substrate spaced apart from the test transistor, wherein at least one metal interconnection among the multi-level metal interconnections is a spiral metal interconnection.

The present disclosure provides a semiconductor structure having a test structure. The semiconductor structure includes a semiconductor substrate, a memory device and a test structure. The memory device is disposed on the semiconductor substrate, and includes a device area and an edge area. The edge area surrounds the device area. The test structure is disposed on the semiconductor substrate, and includes a dummy area, a test edge area and a plurality of unit cells. The test edge area surrounds the dummy area. The plurality of unit cells are disposed in the test edge area, and the dummy area is free of the unit cells. A dimension of the test edge area in a top view is different from a dimension of the edge area in the top view.

A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

A semiconductor testing structure forming method includes: a semiconductor substrate is provided, and the semiconductor substrate includes a plurality of active areas arranged separately; a first conductive wire is formed at a preset distance from the plurality of active areas in the semiconductor substrate, and the first conductive wire is connected with a substrate of a respective active device formed in each of the plurality of active areas; a plurality of first contact holes is formed on the first conductive wire; and a first metal layer is formed on top of each of the plurality of first contact holes to obtain the semiconductor testing structure, where the first metal layer is electrically connected with a first common pad and the first common pad is configured to perform an electric performance test on the semiconductor testing structure.

The present disclosure provides an electrical test structure, a semiconductor structure and an electrical test method. In the electrical test structure, in a first direction, the electrical test structure includes a first layer, an interconnect hole and a second layer arranged in a stack, and the interconnect hole is in contact with the first layer; the second layer includes a body part and a test part, and the test part is connected to the body part; the interconnect hole is configured as, when an offset distance of the interconnect hole relative to a preset position in a second direction is less than a first preset distance, or an offset distance of the interconnect hole relative to the preset position in a third direction is less than a second preset distance, the interconnect hole is spaced apart from the test part.

The present application relates to the field of semiconductors, and discloses a semiconductor device layout structure and a method of forming a semiconductor device. The semiconductor device layout structure includes: an active area layout layer and a plurality of subdevice layout layers located on the active area layout layer, wherein each of the subdevice layout layers includes a gate pattern region, a source pattern region, and a drain pattern region; and the gate pattern regions of at least two of the subdevice layout layers are connected together and form a gate connection pattern region, the source pattern regions of the at least two of the subdevice layout layers are connected together and form a source connection pattern region, the gate connection pattern region is connected to a gate test terminal, and the source connection pattern region is connected to a source test terminal.