A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

A method of detecting or monitoring process electrical charge produced during fabrication of an integrated circuit (IC) on a semiconductor wafer includes fabricating a process charge detection circuit on or in the semiconductor wafer, including: a victim isolation well, a gate oxide disposed on or in the victim isolation well, an aggressor isolation well electrically connected with the victim isolation well via the gate oxide, a victim antenna electrically connected with the victim isolation well and together with the victim isolation well defining a victim RC time constant, and an aggressor antenna electrically connected with the aggressor isolation well and together with the aggressor isolation well defining an aggressor RC time constant that is different from the victim RC time constant. Process charge is detected using the process charge detection circuit. The detecting comprises measuring an electrical parameter of the gate oxide.

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. There are test circuit sites in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Selection circuitry is positioned within the scribe lines. The selection circuitry is connected to test circuits in the scribe lines. The selection circuitry operates to enable voltage control at a single test circuit while disabling all other test circuits.

The present disclosure provides a target and a method of performing overlay measurements on a target. The target includes an array of cells comprising a first cell, a second cell, a third cell, and a fourth cell. Each cell includes a periodic structure with a pitch. The periodic structure includes a first section and a second section, separated by a first gap. The target further includes an electron beam overlay target, such that electron beam overlay measurements, advanced imaging metrology, and/or scatterometry measurements can be performed on the target.

A test device includes semiconductor substrate, gate lines disposed on an upper surface of the semiconductor substrate and extending in a first direction parallel to the upper surface, a test element group including test transistors defined by the gate lines and by active regions extending in a second direction perpendicular to the first direction and intersecting the gate lines, and metal wirings disposed on the semiconductor substrate and electrically connected to the active regions and/or the gate lines, and a test circuit electrically connected to the metal wirings and configured to measure resistance of the test transistors. The gate lines include first gate lines and second gate lines disposed alternately, with the spacing between first gate lines and second gate lines alternating between a first distance and a second distance greater than the first distance.

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

The present disclosure provides a pad structure and a testkey structure and a testing method for a semiconductor device. The pad structure includes: an insulating dielectric layer formed on a substrate; a metal interconnection structure formed in the insulating dielectric layer, the metal interconnection structure comprising a first section and a second section, which are insulated from each other; and a pad formed on the top of the insulating dielectric layer so as to be exposed therefrom at least at its top surface, electrically connected to the first section, and insulated from the second section. With this disclosure, reduced capture of plasma is achievable, mitigating adverse impact of plasma on the semiconductor device.

Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.