The present disclosure relates to the technical field of integrated circuits, and provides a test structure of an integrated circuit, to solve the technical problem of difficulty in measuring electrical parameters of the integrated circuit. The test structure of an integrated circuit includes: a first P-type heavily doped region, a second P-type heavily doped region, and an N-type heavily doped region. There is a first distance between the first P-type heavily doped region and the second P-type heavily doped region, and there is a second distance between the second P-type heavily doped region and the N-type heavily doped region. Electrical parameters of the integrated circuit are obtained by adjusting at least one of the first distance and the second distance.

Embodiments of the present disclosure relate to the technical field of integrated circuits, and specifically to a test structure of an integrated circuit. The embodiments of the present disclosure are intended to solve the problem that the related art does not provide a test structure of an integrated circuit. In the test structure of an integrated circuit provided in the present disclosure, there is a first distance between a first N-type heavily doped region and a second N-type heavily doped region, and there is a second distance between the second N-type heavily doped region and a first P-type heavily doped region; electrical parameters of the integrated circuit corresponding to the test structure are tested by adjusting at least one of the first distance and the second distance.

A semiconductor device may include function circuits and a test line structure beside the function circuits. The test line structure includes standard cell circuit blocks including a first components and environment circuit regions between the standard cell circuit blocks. The environment circuit regions include second components. The first components are different from the second components in structure, arrangement or a combination thereof.

A package structure includes a core substrate including a substrate base including a plurality of first cavities and a plurality of second cavities, a plurality of blocks in the plurality of second cavities; and a plurality of bridge structures that extend between each of the plurality of blocks and the substrate base, a plurality of semiconductor chips in the plurality of first cavities, and a molding layer configured to cover the core substrate and the plurality of semiconductor chips, a portion of the molding layer being in the plurality of first cavities and the plurality of second cavities.

One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

A test method for a semiconductor device having a package with airtight space, which is formed between a substrate wafer on which an element is formed and a cap wafer which is provided being opposite to the substrate wafer, comprises an applying water process in which the semiconductor device is exposed to high moisture atmosphere and cooled and a leak discrimination process in which power is supplied to the element which is formed on the substrate wafer and leak of the package is discriminated by detecting a sound wave which is generated by the semiconductor device.

An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

A stress measuring structure, including a substrate, a support layer, a material layer, and multiple marks, is provided. The support layer is disposed on the substrate. The material layer is disposed on the support layer. There is a trench exposing the support layer in the material layer. The material layer includes a main body and a cantilever beam. The trench is located between the cantilever beam and the main body and partially separates the cantilever beam from the main body. One end of the cantilever beam is connected to the main body. The marks are located on the main body and the cantilever beam.